參數(shù)資料
型號(hào)： PCI4515ZHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED
中文描述： 單插槽CardBus控制器，它集成
文件頁(yè)數(shù)： 81/216頁(yè)
文件大?。?/td> 1138K
代理商： PCI4515ZHK
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415
4.25 Bridge Control Register
The bridge control register provides control over various PCI4515 bridging functions. See Table 47 for a complete
description of the register contents.
Bit
Name
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bridge control
RW
1
R
0
R
0
R
0
R
0
R
0
RW
0
RW
1
RW
0
RW
1
RW
0
R
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Default:
Bridge control
3Eh (Function 0)
Read-only, Read/Write
0340h
Table 47. Bridge Control Register Description
BIT
1511
SIGNAL
RSVD
TYPE
R
FUNCTION
These bits return 0s when read.
Write posting enable. Enables write posting to and from the CardBus socket. Write posting enables the
posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not.
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is
encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
PCI interrupt IREQ routing enable. This bit is used to select whether PC Card functional interrupts are
routed to PCI interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCA registers.
CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST
signal can also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
1 = CRST is asserted (default).
This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
Master abort mode. This bit controls how the PCI4515 controller responds to a master abort when the
PCI4515 controller is an initiator on the CardBus interface.
0 = Master aborts not reported (default).
1 = Signal target abort on PCI and signal SERR, if enabled.
This bit returns 0 when read.
VGA enable. This bit affects how the PCI4515 controller responds to VGA addresses. When this bit is set,
accesses to VGA addresses are forwarded.
ISA mode enable. This bit affects how the PCI4515 controller passes I/O cycles within the 64-Kbyte ISA
range. When this bit is set, the PCI4515 controller does not forward the last 768 bytes of each 1K I/O range
to CardBus.
CSERR enable. This bit controls the response of the PCI4515 controller to CSERR signals on the CardBus
bus.
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR.
CardBus parity error response enable. This bit controls the response of the PCI4515 to CardBus parity
errors.
0 = CardBus parity errors are ignored (default).
1 = CardBus parity errors are reported using CPERR.
10
POSTEN
RW
9
PREFETCH1
RW
8
PREFETCH0
RW
7
INTR
RW
6
CRST
RW
5
MABTMODE
RW
4
RSVD
R
3
VGAEN
RW
2
ISAEN
RW
1
CSERREN
RW
0
CPERREN
RW
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
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