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參數(shù)資料
| 型號(hào)： | PCI4515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| 中文描述： | 單插槽CardBus控制器，它集成 |
| 文件頁數(shù)： | 168/216頁 |
| 文件大小： | 1138K |
| 代理商： | PCI4515ZHK |
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818
8.21 Interrupt Event Register
The interrupt event set/clear register reflects the state of the various PCI4515 interrupt sources. The interrupt bits
are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the
set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.
This register is fully compliant with the
1394 Open Host Controller Interface Specification
, and the PCI4515 controller
adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the
bit-wise AND function of the interrupt event and interrupt mask registers. See Table 815 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Interrupt event
Type
R
RSC
RSC
R
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Default
0
X
0
0
0
X
X
X
X
X
X
X
X
0
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Interrupt event
Type
RSCU
R
R
R
R
R
RSCU
RSCU
RU
RU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Default
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Interrupt event
80h
84h
set register
clear register [returns the content of the interrupt event register bit-wise ANDed with
the interrupt mask register when read]
Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
XXXX 0XXXh
Type:
Default:
Table 815. Interrupt Event Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3130
RSVD
R
Reserved. Bits 31 and 30 return 0 when read.
29
SoftInterrupt
RSC
Bit 29 is used by software to generate a PCI4515 interrupt for its own use.
28
RSVD
R
Reserved. Bit 28 returns 0 when read.
27
ack_tardy
RSCU
Bit 27 is set to 1 when bit 29 (AckTardyEnable) in the host controller control register at OHCI offset
50h/54h (see Section 8.16) is set to 1 and any of the following conditions occur:
a. Data is present in a receive FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending responses.
c. The PCI4515 controller sent an ack_tardy acknowledgment.
26
phyRegRcvd
RSCU
The PCI4515 controller has received a PHY register data byte which can be read from bits 2316
in the PHY layer control register at OHCI offset ECh (see Section 8.33).
25
cycleTooLong
RSCU
If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 8.31) is set to
1, then this indicates that over 125
μ
s has elapsed between the start of sending a cycle start packet
and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is cleared by this event.
24
unrecoverableError
RSCU
This event occurs when the PCI4515 controller encounters any error that forces it to stop operations
on any or all of its subunits, for example, when a DMA context sets its dead bit to 1. While bit 24 is
set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from being set
to 1.
23
cycleInconsistent
RSCU
A cycle start was received that had values for the cycleSeconds and cycleCount fields that are
different from the values in bits 3125 (cycleSeconds field) and bits 2412 (cycleCount field) in the
isochronous cycle timer register at OHCI offset F0h (see Section 8.34).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI4520 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL-SOCKET PC CARD AND INTEGRATED 1394A-2000 OHCI TWO-PORT PHY/LINK-LAYER CONTROLLER |
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| PCI4520ZHK | 制造商:Texas Instruments 功能描述: |
| PCI-471LF | 制造商:PROTECHSYSTEMS 制造商全稱:PROTECHSYSTEMS 功能描述:PCI ULV Celeron M CPU Card |
| PCI5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse |
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