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參數(shù)資料
| 型號： | PCI4515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| 中文描述： | 單插槽CardBus控制器，它集成 |
| 文件頁數(shù)： | 198/216頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | PCI4515ZHK |
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94
9.4
Link Enhancement Register
This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI
offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM,
if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must
be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see
Section 8.16). See Table 93 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Link enhancement
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Link enhancement
Type
RSC
R
RSC
RSC
R
RSC
R
RSC
RSC
R
R
R
R
R
RSC
R
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Link enhancement
A88h
A8Ch
Read/Set/Clear, Read-only
0000 0000h
set register
clear register
Type:
Default:
Table 93. Link Enhancement Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3116
RSVD
R
Reserved. Bits 3116 return 0s when read.
15
dis_at_pipeline
RSC
Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled. The default value
for this bit is 0.
14
RSVD
R
Reserved. Bit 14 defaults to 0 and must remain 0 for normal operation of the OHCI core.
1312
atx_thresh
RSC
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte
threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on
the average PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger
than the AT threshold, then the remaining data must be received before the AT FIFO is emptied;
otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result,
the link then commences a store-and-forward operation. It waits until it has the complete packet in
the FIFO before retransmitting it on the second attempt, to ensure delivery.
An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data
will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold
to 2K results in only complete packets being transmitted.
Note that this controller always uses a store-and-forward operation when the asynchronous transmit
retries register at OHCI offset 08h (see Section 8.3) is cleared.
11
RSVD
R
Reserved. Bit 11 returns 0 when read.
10
enab_mpeg_ts
RSC
Enable MPEG timestamp enhancements. When bit 10 is set to 1, the enhancement is enabled for
MPEG transmit streams (FMT = 20h). The default value for this bit is 0.
9
RSVD
R
Reserved. Bit 9 returns 0 when read.
These bits are cleared only by the assertion of GRST.
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