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| 型號(hào)： | PCI4515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| 中文描述： | 單插槽CardBus控制器，它集成 |
| 文件頁(yè)數(shù)： | 37/216頁(yè) |
| 文件大?。?/td> | 1138K |
| 代理商： | PCI4515ZHK |
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219
Table 215. IEEE 1394 Physical Layer Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
CNA
P18
I/O
Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage.
If it is not used, then this terminal must be strapped either to DVDD or GND through a resistor. The CNA
terminal can be disabled by setting bit 7 (CNAOUT) of the PCI PHY control register at offset ECh in the PCI
configuration space (see Section 7.20,
PCI PHY Control Register
). This bit is loaded by the serial EEPROM.
If an EEPROM is implemented and CNA functionality is needed, then the appropriate bit in the serial
EEPROM must be cleared as defined in Table 39.
Cable power status input. This terminal is normally connected to cable power through a 400-k
resistor.
This circuit drives an internal comparator that is used to detect the presence of cable power. If CPS is not
used to detect cable power, then this terminal must be pulled to GND.
CPS
R12
I
PC0
PC1
PC2
U12
V12
W12
I
Power class programming inputs. On hardware reset, these inputs set the default value of the power class
indicated during self-ID. Programming is done by tying these terminals high or low.
R0
R1
T18
T19
Current-setting resistor terminals. These terminals are connected to an external resistance to set the
internal operating currents and cable driver output currents. A resistance of 6.34 k
±
1% is required to meet
the IEEE Std 1394-1995 output voltage limits.
TPA0P
TPA0N
V14
W14
I/O
Twisted-pair cable A differential signal terminals. Board trace lengths from each pair of positive and negative
differential signal pins must be matched and as short as possible to the external load resistors and to the
cable connector. For an unused port, TPA+ and TPA can be left open.
TPBIAS0
R13
I/O
Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the
twisted-pair cable drivers and receivers and for signaling to the remote nodes that there is an active cable
connection. This pin must be decoupled with a 1.0-
μ
F capacitor to ground.
Twisted-pair cable B differential signal terminals. Board trace lengths from each pair of positive and negative
differential signal pins must be matched and as short as possible to the external load resistors and to the
cable connector. For an unused port, TPB+ and TPB must be pulled to ground.
TPB0P
TPB0N
V13
W13
I/O
XI
XO
R19
R18
Crystal oscillator inputs. These pins connect to a 24.576-MHz parallel resonant fundamental mode crystal.
The optimum values for the external shunt capacitors are dependent on the specifications of the crystal
used (see
Section 3.9.2,
Crystal Selection
). An external clock input can be connected to the XI terminal.
When using an external clock input, the XO terminal must be left unconnected, and the clock must be
supplied before the controller is taken out of reset. Refer to Section 3.9.2 for the operating characteristics
of the XI terminal.
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