
PEB 22554
Operational Description E1
Semiconductor Group
112
09.98
(1024 bits) less than 3 zeros for each doubleframe period (512
bits).
Recovery: The alarm will be cleared if within two consecutive
doubleframe periods 3 or more zeros for each period of 512 bits
will be detected.
FRS…
Force Resynchronization
A transition from low to high will initiate a resynchronization procedure
of the pulse frame and the CRC-multiframe (if enabled via bit
FMR2.RFS1) starting directly after the old framing candidate.
SIM…
Alarm Simulation
0…
Normal operation.
1…
Initiates internal error simulation of AIS, loss of signal, loss of
synchronization, remote alarm, slip, framing errors, CRC
errors, and code violations. The error counters FEC, CVC,
CEC1 will be incremented.
Framer Mode Register 1 (Read/Write)
Value after RESET: 00
H
MFCS…
Multiframe Force Resynchronization
Only valid if CRC multiframe format is selected (FMR2.RFS1/0=10).
A transition from low to high will initiate the resynchronization
procedure for CRC-multiframe alignment without influencing
doubleframe synchronous state. In case, “Automatic Force
Resynchronization” (FMR1.AFR) is enabled and multiframe
alignment can not be regained, a new search of doubleframe (and
CRC multiframe) is automatically initiated.
AFR…
Automatic Force Resynchronization
Only valid if CRC multiframe format is selected (FMR2.RFS1/0=10).
If this bit is set, a search of doubleframe alignment is automatically
initiated if two multiframe patterns with a distance of n
×
2 ms have
not been found within a time interval of 8 ms after doubleframe
alignment has been regained or command FMR1.MFCS has been
issued.
7
0
FMR1
MFCS
AFR
ENSA
PMOD
XFS
ECM
SSD0
XAIS
(x1D)