
Semiconductor Group
342
09.98
PEB 22554
Operational Description T1 / J1
Framer Receive Status Register 1 (Read)
EXZD…
Excessive Zeros Detected
Significant only if excessive zeros detection is enabled
(FMR2.EXZE=1).
Set after detecting of more than 7 (B8ZS code) or more than 15 (AMI
code) contiguous zeros in the received bit stream. This bit is cleared
when read.
PDEN…
Pulse Density Violation Detected
The pulse density of the received data stream is below the
requirement defined by ANSI T1. 403 or more than 14 consecutive
zeros are detected. With the violation of the pulse density this bit will
be set and will remain active until it is read. Reading the register will
clear this bit. (Clear on Read).
Additionally an interrupt status ISR0.PDEN is generated with the
rising edge of PDEN.
LLBDD…
Line Loop Back Deactuation Signal Detected
This bit is set to one in case the LLB deactuate signal is detected and
then received over a period of more than 33,16 msec with a bit error
rate less than 1/100. The bit remains set as long as the bit error rate
does not exceed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit will cause a LLBSC interrupt.
LLBAD…
Line Loopback Actuation Signal Detected / PRBS Status
Depending on bit LCR1.EPRM the source of this status bit changed.
LCR1.EPRM=0: This bit is set to one in case the LLB actuate signal
is detected and then received over a period of more than 33,16 msec
with a bit error rate less than 1/100. The bit remains set as long as the
bit error rate does not exceed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit will cause a LLBSC interrupt.
7
0
FRS1
EXZD
PDEN
LLBDD
LLBAD
XLS
XLO
(x4D)