Semiconductor Group
275
09.98
PEB 22554
Operational Description T1 / J1
(MODE.HRAC/BRAC), an automatic switching between HDLC and BOM mode is
enabled. Storing of received DL bit information in the RFIFO of the signaling controller
and transmitting the XFIFO contents in the DL bit positions is enabled by
CCR1.EDLX/EITS = 10. After Reset or software-reset (CMDR.RRES) the QuadFALC
operates in HDLC mode. If eight or more consecutive ones are detected, the BOM mode
is entered. Upon detection of a flag in the data stream, the QuadFALC switches back to
HDLC-mode. Operating in BOM-mode, the QuadFALC may receive an HDLC frame
immediately, i.e. without any preceding flags.
In BOM-mode, the following byte format is assumed (the left most bit is received first).
111111110xxxxxx0
The QuadFALC uses the FF
H
byte for synchronization, the next byte is stored in RFIFO
(first bit received: LSB) if it starts and ends with a ‘0’. Bytes starting and ending with a ‘1’
are not stored. If there are no 8 consecutive one’s detected within 32 bits, an interrupt is
generated. However, byte sampling is not stopped.
Byte sampling in BOM Mode
a)
b)
Three different BOM reception modes may be programmed (CCR1.BRM, CCR2.RBFE).
10 byte packets:
CCR1.BRM = 0
After storing 10 bytes in RFIFO the receive status byte marking a BOM frame
(RSIS.HFR) is added as the eleventh byte and an interrupt (ISR0.RME) is generated.
The sampling of data bytes continues and interrupts are generated every 10 bytes until
an HDLC flag is detected.
1111
1111 1111 0011 0100 1111 1111 0011 0100 1110 1111 0011 0100 1101 1111
sync
not stored
new sync
1.byte
stored
1.corrupted
sync
2.byte
stored
2.corrupted
sync
corrupted
sync
1111
1111 0111 0110 1101 1111 0111 0110 1111 1111 0111 0110 0111 1111
sync
1.byte
stored
1.corrupted
byte
2.byte
stored
2.sync
3.byte
stored
3.corrupted
sync