
Semiconductor Group
360
09.98
PEB 22554
Operational Description T1 / J1
MFAR…
Multiframe Alignment Recovery
Set when the framer has reached multiframe alignment in F12 or F72
format. With the negative transition of bit FRS0.LMFA this bit will be
set. It will be set during alarm simulation.
LMFA…
Loss of Multiframe Alignment
Set when the framer has lost the multiframe alignment in F12 or F72
format. With the positive transition of bit FRS0.LMFA this bit will be
set. It will be set during alarm simulation.
AIS…
Alarm Indication Signal (Blue Alarm)
This bit is set when an alarm indication signal is detected and bit
FRS0.AIS is set. If GCR.SCI is set high this interrupt status bit will be
activated with every change of state of FRS0.AIS.
It will be set during alarm simulation.
LOS…
Loss of Signal (Red Alarm)
This bit is set when a loss of signal alarm is detected in the received
data stream and FRS0.LOS is set. If GCR.SCI is set high this interrupt
status bit will be activated with every change of state of FRS0.LOS.
It will be set during alarm simulation.
RAR…
Remote Alarm Recovery
Set if a remote alarm (yellow alarm) is cleared and bit FRS0.RRA is
reset. It is set also after alarm simulation is finished and no remote
alarm is detected.
RA…
Remote Alarm
A remote alarm (yellow alarm) is detected. Set with the rising edge of
bit FRS0.RRA. It will be set during alarm simulation.
Interrupt Status Register 3 (Read)
All bits are reset when ISR3 is read.
If bit GCR.VIS is set to ‘1’, interrupt statuses in ISR3 may be flagged although they are
masked via register IMR3. However, these masked interrupt statuses neither generate a
signal on INT, nor are visible in register GIS.
7
0
ISR3
ES
SEC
LLBSC
RSN
RSP
(x6B)