
PEB 22554
Operational Description E1
Semiconductor Group
137
09.98
ignored for the remaining time of the 488 nsec or for the remaining
channel phases. The channel phases are selectable with these bits.
000 …data active in channel phase 1, valid if system data rate is
16 / 8 / 4 MBit/s
001 …data active in channel phase 2, valid if system data rate is
16 / 8 / 4 MBit/s
010 …data active in channel phase 3, valid if data rate is 16 / 8 MBit/s
011 …data active in channel phase 4, valid if data rate is 16 / 8 MBit/s
100 …data active in channel phase 5 , valid if data rate is 16 MBit/s
101 …data active in channel phase 6 , valid if data rate is 16 MBit/s
110 …data active in channel phase 7, valid if data rate is 16 MBit/s
111 …data active in channel phase 8 , valid if data rate is 16 MBit/s
System Interface Control 3 (Read/Write)
Value after RESET: 00
H
CASMF…
CAS Multiframe Begin Marker
0…The time-slot 0 multiframe begin is asserted on pin RP(A-D) / pin
function RMFB.
1…The time-slot 16 CAS multiframe begin is asserted on pin RP(A-
D) / pin function RMFB.
RESX…
Rising Edge Synchronous Pulse Transmit
Depending on this bit all transmit system interface data and marker
are clocked off or sampled with the selected active edge.
0…
SYPX is latched with the first falling (active) edge of the SCLKX
clock.
1…
SYPX is latched with the first rising (active) edge of the SCLKX
clock.
The SYPX pin function is selected by PC(1-4).XC(2-0) = 0000.
RESR…
Rising Edge Synchronous Pulse Receive
Depending on this bit all receive system interface data and marker are
clocked off with the selected active edge.
7
0
SIC3
CASMF
RESX
RESR
TTRF
DAF
(x40)