
Semiconductor Group
357
09.98
PEB 22554
Operational Description T1 / J1
The complete message length can be determined reading the RBCH,
RBCL registers, the number of bytes currently stored in RFIFO is
given by RBC4-0. Additional information is available in the RSIS
register.
RFS / BIV …
Receive Frame Start
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After a RFS
interrupt, the contents of RAL1and RSIS.3-1 are valid and can be
read by the CPU.
BOM Frame Invalid
Only valid if CCR2.RBFE is set.
When the BOM receiver left the valid BOM status (detecting 7 out of
10 equal BOM frames) this interrupt is generated.
ISF…
Incorrect Sync Format
The QuadFALC could not detect eight consecutive one’s within 32
bits in BOM mode. Only valid if BOM receiver has been activated.
RMB…
Receive Multiframe Begin
This bit is set with the beginning of a received multiframe of the
receive line timing.
RSC…
Received Signaling Information Changed
This interrupt bit is set during each multiframe in which signaling
information on at least one channel changes its value from the
previous multiframe. This interrupt will only occur in the synchronous
state. The registers RS1-12 should be read within the next 3 ms
otherwise the contents may be lost.
CRC6…
Receive CRC6 Error
0…
No CRC6 error occurs.
1…
The CRC6 check of the last received multiframe failed.
PDEN…
Pulse Density violation
The pulse density violation of the received data stream defined by
ANSI T1. 403 is violated. More than 14 consectuive zeros or less than
N ones in each and every time window of 8(N+1) data bits (N=23) are
detected. If GCR.SCI is set high this interrupt status bit will be
activated with every change of state of FRS1.PDEN.