
Semiconductor Group
200
09.98
PEB 22554
General Features T1
120 - 123
126 - 129
51 - 54
57 - 60
XP(A-D)1
XP(A-D)2
XP(A-D)3
XP(A-D)4
I/O + PU
I + PU
I + PU
Transmit Multifunction Port A-D
Depending on programming of bits
PC(1-4).XPC(2-0) this multifunction ports carries
information to the system interface or from the
system to the QuadFALC. After Reset these ports
are configured to inputs. With the selection of the
pinfunction the in/output configuration is also
achieved. Depending on bit SIC3.RESX all
outputs / inputs of the transmit system interface
are updated / sampled with the rising or falling
edge of SCLKX.
Synchronous Pulse Transmit (SYPX)
Defines the beginning of time-slot 0 at system
highway port XDI in conjunction with the values of
registers XC0/1. In system interface multiplex
mode SYPX has to be provided at port XPA1 for
all 4 channels and defines the beginning of
time-slot 0 on port XDI1/XSIG1. Enabled with
PC(1-4).XPC(2-0) = 000 (reset configuration).
Pulse Cycle: Integer multiple of 125
μ
s.
Transmit Multiframe Synchronization (XMFS)
Enabled with PC(1-4).XPC(2-0) = 001 this port
defines the frame and multiframe begin on the
transmit system interface ports XDI and XSIG.
Depending on PC5.CXMFS the signal on XMFS is
active high or low. For correct operation of XMFS
no SYPX pin function should be selected for the
remaining multifunction ports of the same channel.
In system interface multiplex mode XMFS has to
be provided at port XPB1 for all 4 channels.
Note:
A new multiframe position has been settled
at least one multiframe after pulse XMFS has
been supplied.
Pin Definitions and Function
(cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Function