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| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數(shù)： | 100/102頁 |
| 文件大?。?/td> | 920K |
| 代理商： | PENTIUM III CPU |
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100
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
SLP#
I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SMI#
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
STPCLK#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
TCK
I
The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
O
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI
I
The TESTHI signal must be connected to a 2.5 V power source through a 1-100 k
resistor for proper processor operation.
THERMDN
O
Thermal Diode Cathode. Used to calculate core temperature. See
Section 4.1
.
THERMDP
I
Thermal Diode Anode. Used to calculate core temperature. See
Section 4.1
.
THERMTRIP#
O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active. There is no
hysteresis built into the thermal sensor itself; as long as the die temperature drops
below the trip level, a RESET# pulse will reset the processor and execution will
continue. If the temperature has not dropped below the trip level, the processor will
continue to drive THERMTRIP# and remain stopped.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TRDY#
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset. This can be done with a 680 ohm pull-
down resistor.
VID[4:0]
O
The VID[4:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V
SS
on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See
Table 3
for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
Table 41. Signal Description
(Sheet 7 of 7)
Name
Type
Description
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