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參數(shù)資料
| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數(shù)： | 47/102頁 |
| 文件大?。?/td> | 920K |
| 代理商： | PENTIUM III CPU |
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Datasheet
47
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
3.3.1
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10 percent of the total signal swing (V
HI
- V
LO
)
above and below its final value. A signal should be within the settling limits of its final value, when
either in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
Figure 16. Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance
Figure 17. Signal Overshoot/Undershoot, Settling Limit, and Ringback
1
0.7V Clk Ref
Clock
Time
V
start
V
REF
- 0.2
V
REF
V
REF
+ 0.2
Note: High to low case is analogous
τ
α
δ
ρ
φ
Undershoot
Overshoot
Settling Limit
Settling Limit
Rising-Edge
Ringback
Falling-Edge
Ringback
V
LO
V
SS
Time
000767
V
HI
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