參數(shù)資料
型號(hào)： pentium III CPU
廠商： Intel Corp.
英文描述： Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器)
中文描述： 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242）
文件頁(yè)數(shù)： 28/102頁(yè)
文件大?。?/td> 920K
代理商： PENTIUM III CPU
28
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This specification applies to Pentium
III processors. For baseboard compatibility information on Pentium II
processors, refer to the Pentium
II Processor at 350, 400 and 450 MHz datasheet (Order Number 243657).
3. V
CCCORE
and Icc
supply the processor core.
4. A variable voltage source should exist on all systems in the event that a different voltage is required. See
Section 2.6 and Table 1 for more information.
5. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation
to the processor.
6. V
must be held to 1.5 V ±9%. It is recommended that V
be held to 1.5 V ±3% while the Pentium III
processor system bus is idle. This is measured at the processor edge fingers across a 20 MHz bandwidth.
7. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the
bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops (and
impedance discontinuities) across the connector, processor edge fingers, and to the processor core.
V
CCCORE
must return to within the static voltage specification within 100
μ
s after a transient event; see the
VRM 8.2 DC-DC Converter Design Guidelines (Order Number 243773) for further details.
8. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The
requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the
processor edge fingers and to the processor core. V
CCCORE
must return to within the static voltage
specification within 100
μ
s after a transient event.
9. V
CCL2
/V
CC3.3
and I
/I
supply the second level cache (“Discrete” cache type only). Unless otherwise
noted, this specification applies to all Pentium III processor cache sizes. Systems should be designed for
these specifications, even if a smaller cache size is used.
10.Max I
CC
measurements are measured at V
CC
max voltage, maximum temperature, under maximum signal
loading conditions. The Max Icc currents specified do not occur simultaneously under the stress
measurement condition.
11.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of V
CCCORE
(V
CCCORE_TYP
). In this case, the maximum current level for the regulator, Icc
, can be reduced from
the specified maximum current Icc
CORE _MAX
and is calculated by the equation:
Icc
CORE_REG
= Icc
CORE_MAX
×
V
CCCORE_TYP
/ (V
CCCORE_TYP
+ V
CCCORE
Tolerance, Transient)
12.The current specified is the current required for a single Pentium III processor. A similar amount of current is
drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended
termination is used (see
Section 2.1
).
13.The current specified is also for AutoHALT state.
14.Maximum values are specified by design/characterization at nominal V
CCCORE
and nominal V
CCL2
/V
CC3.3
.
15.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
16.dI
CC
/dt specifications are measured and specified at the SC242 connector pins.
17.Vcc
and I
CC5
are not used by the Pentium III processors. The V
CC5
supply is used for the test equipment
and tools.
18.This specification applies to the Pentium
III processor with CPUID=067xh.
19.This specification applies to the Pentium
III processor with CPUID=068xh.
20.Max I
measurements are measured at V
CC
nominal voltage, maximum temperature, under maximum
signal loading conditions. The Max Icc currents specified do not occur simultaneously under the stress
measurement condition.
21..This specification applies to the Pentium
III processor with CPUID=0683h operating at 1.0 GHz.
dI
CCL2
/dt
L2 cache power supply
current slew rate
Termination current slew
rate
5 V supply voltage
I
CC
for 5 V supply voltage
1
A/
μ
s
14, 15, 16, 18
dI
CCV
TT
/dt
8
A/μs
14, 15, See
Table 11
5 V ±5%
16, 17
17
V
CC5
I
CC5
4.75
5.00
1.0
5.25
V
A
Table 8. Voltage and Current Specifications (Continued)
Symbol
Parameter
Core Freq
Min
Typ
Max
Unit
Notes
1
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