參數(shù)資料
型號： pentium III CPU
廠商： Intel Corp.
英文描述： Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器)
中文描述： 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242）
文件頁數(shù)： 98/102頁
文件大小： 920K
代理商： PENTIUM III CPU
98
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
LOCK#
I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of
the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
PICCLK
I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICD[1:0]
I/O
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.
PRDY#
O
The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PREQ#
I
The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
PWRGOOD
I
The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The
processor requires this signal to be a clean indication that the clocks and power
supplies (V
CCCORE
, etc.) are stable and within their specifications. Clean implies
that the signal will remain low (capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high (2.5 V) state.
The figure below illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in
Table 15
, and be followed by a 1 ms RESET#
pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
PWRGOOD Relationship at Power-On
REQ[4:0]#
I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
Table 41. Signal Description
(Sheet 5 of 7)
Name
Type
Description
BCLK
PWRGOOD
RESET#
D0026-00
1 msec
V
IH,min
V
CC
,
V
CCP
,
V
REF
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