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| 型號(hào)： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數(shù)： | 31/102頁 |
| 文件大小： | 920K |
| 代理商： | PENTIUM III CPU |
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Datasheet
31
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
the
Pentium
III
Processor I/O Buffer Models
on Intel’s Developer’s Website
(http://developer.intel.com.) AGTL+ layout guidelines are also available in AP-906,
100 MHz
AGTL+ Layout Guidelines for the Pentium
III
Processor and Intel
440BX AGPset
(Order
Number 245086) or the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
1. Unless otherwise noted, all specifications in this table apply to all Pentium
III processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core
pins.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.
4. The internal core clock frequency is derived from the Pentium III processor system bus clock. The system
bus clock to core clock ratio is fixed for each processor. Individual processors will only operate at their
specified system bus frequency, either 100MHz or 133 MHz.
Table 13
shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the
rising edges of adjacent BCLKs crossing 1.25 V at the processor core pin
. The jitter
present must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than
500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer.
8. Not 100% tested. Specified by design characterization as a clock driver requirement.
9. The average period over a 1uS period of time must be greater than the minimum specified period.
10.This specification applies to the Pentium III processor with a system bus frequency of 100 MHz
.
11.This specification applies to the Pentium III processor with a system bus frequency of 133 MHz
.
Table 12. System Bus AC Specifications (Clock) at Processor Core Pins
1, 2, 3
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
100.00
133.33
MHz
MHz
4, 10
4, 11
4, 5, 10
4, 5, 11
T1: BCLK Period
10.0
7.5
ns
ns
7
7
T2: BCLK Period Stability
±250
ps
7
7, 9
T3: BCLK High Time
2.5
1.4
ns
ns
7
7
@>2.0 V, 10
@>2.0 V, 11
@<0.5 V
6, 10
@<0.5 V
6, 11
(0.5 V–2.0 V)
8, 10, 11
(2.0 V–0.5 V)
8, 10, 11
T4: BCLK Low Time
2.4
1.4
ns
ns
7
7
T5: BCLK Rise Time
0.4
1.60
ns
7
T6: BCLK Fall Time
0.4
1.60
ns
7
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