TM Family Datasheet Page 26 of 77 August 2009 – Re" />
參數(shù)資料
型號(hào)： PI7C9X20303ULAZPE
廠商： Pericom
文件頁(yè)數(shù)： 19/77頁(yè)
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝： 168
系列： UltraLo™
應(yīng)用： 封裝開關(guān)，3 端口/3 線道
接口： PCI Express
封裝/外殼： 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝： 132-TQFN-EP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 26 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
ADDRESS
PCI CFG OFFSET
DESCRIPTION
E0h (Port1)
E0h: Bit [24]
F0h (Port 1)
F0h: Bit [28]
80h (Port 1)
80h: Bit[21]
ECh (Port 1)
ECh: Bit [25:24]
84h (Port 1)
84h: Bit [14:13]
PCIe Capability Slot Implemented for Port 1
Bit [0]: When set, the slot is implemented for Port 1
Slot Clock Configuration for Port 1
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 1
Bit [2]: When set, the DSI is required
Port Number for Port 1
Bit [5:4]: It represents the logic port numbering for physical port
1
PMCSR Data Scale for Port 1
Bit [7:6]: It represents the PMCSR Data Scale for physical port 1
22h
154h (Port 1)
154h: Bit [7:1]
VC0 TC/VC Map for Port 1
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
E0h (Port 2)
E0h: Bit [24]
F0h (Port 2)
F0h: Bit [28]
80h (Port 2)
80h: Bit[21]
ECh (Port 2)
ECh: Bit [25:24]
84h (Port 2)
84h: Bit [14:13]
PCIe Capability Slot Implemented for Port 2
Bit [0]: When set, the slot is implemented for Port 2
Slot Clock Configuration for Port 2
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 2
Bit [2]: When set, the DSI is required
Port Number for Port 2
Bit [5:4]: It represents the logic port numbering for physical port
2
PMCSR Data Scale for Port 2
Bit [7:6]: It represents the PMCSR Data Scale for physical port 2
24h
154h (Port 2)
154h: Bit [7:1]
VC0 TC/VC Map for Port 2
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
32h
F4h (Port 1)
F4h: Bit [15:0]
Slot Capability 0 of Port 1
Bit [15:0]: Mapping to the low word of slot capability register
34h
F4h (Port 2)
F4h: Bit [15:0]
Slot Capability 0 of Port 2
Bit [15:0]: Mapping to the low word of slot capability register
42h
F4h (Port 1)
F4h: Bit [31:16]
Slot Capability 1 of Port 1
Bit [15:0]: Mapping to the high word of slot capability register
44h
F4h (Port 2)
F4h: Bit [31:16]
Slot Capability 1 of Port 2
Bit [15:0]: Mapping to the high word of slot capability register
50h
84h (Port 0)
84h: Bit [3]
80h (Port 0)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 0
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 0
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
51h
84h (Port 0)
84h: Bit [31:24]
Power Management Data for Port 0
Bit [15:8]: read only as Data register
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參數(shù)描述
PI7C9X20303ULAZPEX 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404GPANBE 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays
PI7C9X20404GPBNBE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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