TM Family Datasheet Page 7 of 77 August 2009 – Rev" />
參數(shù)資料
型號(hào)： PI7C9X20303ULAZPE
廠商： Pericom
文件頁(yè)數(shù)： 67/77頁(yè)
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝： 168
系列： UltraLo™
應(yīng)用： 封裝開(kāi)關(guān)，3 端口/3 線道
接口： PCI Express
封裝/外殼： 132-VFQFN 雙排裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 132-TQFN-EP（10x10）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 7 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
7.2.61
EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only)........................................ 48
7.2.62
EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only)......................................... 49
7.2.63
EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only)................................................ 49
7.2.64
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ............................................................ 49
7.2.65
NEXT ITEM POINTER REGISTER – OFFSET E0h .......................................................................... 49
7.2.66
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h .............................................................. 49
7.2.67
DEVICE CAPABILITIES REGISTER – OFFSET E4h ....................................................................... 50
7.2.68
DEVICE CONTROL REGISTER – OFFSET E8h............................................................................... 51
7.2.69
DEVICE STATUS REGISTER – OFFSET E8h................................................................................... 51
7.2.70
LINK CAPABILITIES REGISTER – OFFSET ECh ............................................................................ 52
7.2.71
LINK CONTROL REGISTER – OFFSET F0h.................................................................................... 53
7.2.72
LINK STATUS REGISTER – OFFSET F0h ........................................................................................ 53
7.2.73
SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h ................................... 54
7.2.74
SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h........................................... 55
7.2.75
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h ............................................... 56
7.2.76
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h. 57
7.2.77
CAPABILITY VERSION – OFFSET 100h .......................................................................................... 57
7.2.78
NEXT ITEM POINTER REGISTER – OFFSET 100h......................................................................... 57
7.2.79
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 57
7.2.80
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 58
7.2.81
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch............................................. 59
7.2.82
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h...................................................... 59
7.2.83
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ......................................................... 60
7.2.84
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h......................... 60
7.2.85
HEADER LOG REGISTER – OFFSET From 11Ch to 128h .............................................................. 61
7.2.86
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET 140h (Upstream Only)
61
7.2.87
CAPABILITY VERSION – OFFSET 140h (Upstream Only) .............................................................. 61
7.2.88
NEXT ITEM POINTER REGISTER – OFFSET 140h (Upstream Only)............................................. 61
7.2.89
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h (Upstream Only) ........................................ 61
7.2.90
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h (Upstream Only) ........................................ 62
7.2.91
PORT VC CONTROL REGISTER – OFFSET 14Ch (Upstream Only)............................................... 62
7.2.92
PORT VC STATUS REGISTER – OFFSET 14Ch (Upstream Only)................................................... 62
7.2.93
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h (Upstream Only)............................ 63
7.2.94
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h (Upstream Only) .............................. 63
7.2.95
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h (Upstream Only).................................... 64
7.2.96
PORT ARBITRATION TABLE REGISTER (0) – OFFSET 180h-1BCh (Upstream Only).................. 64
7.2.97
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER – OFFSET 20Ch .................... 64
7.2.98
CAPABILITY VERSION – OFFSET 20Ch.......................................................................................... 64
7.2.99
NEXT ITEM POINTER REGISTER – OFFSET 20Ch ........................................................................ 65
7.2.100
DATA SELECT REGISTER – OFFSET 210h ................................................................................. 65
7.2.101
POWER BUDGETING DATA REGISTER – OFFSET 214h .......................................................... 65
7.2.102
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ..................................................... 66
8
CLOCK SCHEME .............................................................................................................................................67
9
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER....................................................................................68
9.1
INSTRUCTION REGISTER ......................................................................................................................68
9.2
BYPASS REGISTER .................................................................................................................................68
9.3
DEVICE ID REGISTER.............................................................................................................................68
9.4
BOUNDARY SCAN REGISTER...............................................................................................................69
9.5
JTAG BOUNDARY SCAN REGISTER ORDER......................................................................................69
10 POWER MANAGEMENT ................................................................................................................................71
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參數(shù)描述
PI7C9X20303ULAZPEX 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404GPANBE 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays
PI7C9X20404GPBNBE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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