TM Family Datasheet Page 38 of 77 August 2009 – Re" />
參數(shù)資料
型號： PI7C9X20303ULAZPE
廠商： Pericom
文件頁數(shù)： 32/77頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 132TQFN
標準包裝： 168
系列： UltraLo™
應(yīng)用： 封裝開關(guān)，3 端口/3 線道
接口： PCI Express
封裝/外殼： 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝： 132-TQFN-EP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 38 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
Reset to 80h.
7.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Interrupt Line
RW
Reset to 00h.
7.2.27
INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Interrupt Pin
RO
The Switch implements INTA virtual wire interrupt signals to represent hot-
plug events at downstream ports. The default value on the downstream ports
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
16
Parity Error
Response
RW
0b: Ignore Poisoned TLPs on the secondary interface
1b: Enable the Poisoned TLPs reporting and detection on the secondary
interface
Reset to 0b.
17
S_SERR# enable
RW
0b: Disables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
1b: Enables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
Reset to 0b.
18
ISA Enable
RW
0b: Forwards downstream all I/O addresses in the address range defined by
the I/O Base, I/O Base, and Limit registers
1b: Forwards upstream all I/O addresses in the address range defined by the
I/O Base and Limit registers that are in the first 64KB of PCI I/O address
space (top 768 bytes of each 1KB block)
Reset to 0b.
19
VGA Enable
RW
0: Ignores access to the VGA memory or IO address range
1: Forwards transactions targeted at the VGA memory or IO address range
VGA memory range starts from 000A 0000h to 000B FFFFh
VGA IO addresses are in the first 64KB of IO address space.
AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh.
Reset to 0b. Please note that this bit is reserved in Port 2.
20
VGA 16-bit decode
RW
0b: Executes 10-bit address decoding on VGA I/O accesses
1b: Executes 16-bit address decoding on VGA I/O accesses
Reset to 0b. Please note that this bit is reserved in Port 2.
21
Master Abort Mode
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Secondary Bus Reset
RW
0b: Does not trigger a hot reset on the corresponding PCI Express Port
1b: Triggers a hot reset on the corresponding PCI Express Port
At the downstream port, it asserts PORT_RST# to the attached downstream
device.
At the upstream port, it asserts the PORT_RST# at all the downstream
ports.
Reset to 0b.
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參數(shù)描述
PI7C9X20303ULAZPEX 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404GPANBE 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays
PI7C9X20404GPBNBE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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