TM Family Datasheet Page 6 of 77 August 2009 – Rev" />
參數(shù)資料
型號： PI7C9X20303ULAZPE
廠商： Pericom
文件頁數(shù)： 56/77頁
文件大小： 0K
描述： IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝： 168
系列： UltraLo™
應(yīng)用： 封裝開關(guān)，3 端口/3 線道
接口： PCI Express
封裝/外殼： 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝： 132-TQFN-EP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 6 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
7.2.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................ 34
7.2.9
HEADER TYPE REGISTER – OFFSET 0Ch...................................................................................... 34
7.2.10
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ...................................................................... 34
7.2.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................ 34
7.2.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................ 34
7.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................................... 35
7.2.14
I/O BASE ADDRESS REGISTER – OFFSET 1Ch.............................................................................. 35
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch............................................................................. 35
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch .......................................................................... 35
7.2.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h ................................................................... 36
7.2.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .................................................................. 36
7.2.19
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ..................................... 36
7.2.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h.................................... 36
7.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ......... 37
7.2.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ....... 37
7.2.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h................................................... 37
7.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.................................................. 37
7.2.25
CAPABILITY POINTER REGISTER – OFFSET 34h ......................................................................... 37
7.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................. 38
7.2.27
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 38
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch .............................................................................. 38
7.2.29
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ........................................... 39
7.2.30
NEXT ITEM POINTER REGISTER – OFFSET 80h........................................................................... 39
7.2.31
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h............................................. 39
7.2.32
POWER MANAGEMENT DATA REGISTER – OFFSET 84h ............................................................ 39
7.2.33
PPB SUPPORT EXTENSIONS – OFFSET 84h.................................................................................. 40
7.2.34
DATA REGISTER – OFFSET 84h ......................................................................................................40
7.2.35
MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) .................................... 40
7.2.36
NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) ................................. 41
7.2.37
MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only) .................................. 41
7.2.38
MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only) .................................... 41
7.2.39
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream Port Only) ...................... 41
7.2.40
MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) ........................................... 41
7.2.41
VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only)........................................ 41
7.2.42
NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only) ...................................... 42
7.2.43
VPD REGISTER – OFFSET 9Ch (Upstream Port Only).................................................................... 42
7.2.44
VPD DATA REGISTER – OFFSET A0h (Upstream Port Only)......................................................... 42
7.2.45
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h .................................................. 42
7.2.46
NEXT ITEM POINTER REGISTER – OFFSET A4h .......................................................................... 43
7.2.47
LENGTH REGISTER – OFFSET A4h ................................................................................................ 43
7.2.48
XPIP CSR0 – OFFSET A8h (Test Purpose Only)............................................................................... 43
7.2.49
XPIP CSR1 – OFFSET ACh (Test Purpose Only) .............................................................................. 43
7.2.50
REPLAY TIME-OUT COUNTER – OFFSET B0h .............................................................................. 43
7.2.51
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h....................................................................... 44
7.2.52
SWITCH OPERATION MODE – OFFSET B4h (Upstream Port) ...................................................... 44
7.2.53
SWITCH OPERATION MODE – OFFSET B4h (Downstream Port) ................................................. 45
7.2.54
XPIP CSR2 – OFFSET B8h (Test Purpose Only)............................................................................... 46
7.2.55
TL CSR – OFFSET BCh ..................................................................................................................... 46
7.2.56
SSID/SSVID CAPABILITY ID REGISTER – OFFSET C0h................................................................ 46
7.2.57
NEXT ITEM POINTER REGISTER – OFFSET C0h .......................................................................... 46
7.2.58
SUBSYSTEM VENDOR ID REGISTER – OFFSET C4h .................................................................... 46
7.2.59
SUBSYSTEM ID REGISTER – OFFSET C4h..................................................................................... 47
7.2.60
GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)............................................... 47
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參數(shù)描述
PI7C9X20303ULAZPEX 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404GPANBE 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays
PI7C9X20404GPBNBE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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