TM Family Datasheet Page 41 of 77 August 2009 – Re" />
參數(shù)資料
型號: PI7C9X20303ULAZPE
廠商: Pericom
文件頁數(shù): 36/77頁
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝: 168
系列: UltraLo™
應(yīng)用: 封裝開關(guān),3 端口/3 線道
接口: PCI Express
封裝/外殼: 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝: 132-TQFN-EP(10x10)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 41 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
7.2.36
NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
Pointer points to the Vendor specific capability register (A4h).
Reset to A4h.
7.2.37
MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
16
MSI Enable
RW
0b: The function is prohibited from using MSI to request service
1b: The function is permitted to use MSI to request service and is prohibited
from using its INTx # pin
Reset to 0b.
19:17
Multiple Message
Capable
RO
Read as 000b.
22:20
Multiple Message
Enable
RW
Reset to 000b.
23
64-bit address
capable
RO
0b: The function is not capable of generating a 64-bit message address
1b: The function is capable of generating a 64-bit message address
Reset to 1b.
31:24
Reserved
RO
Reset to 00h.
7.2.38
MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Reserved
RO
Reset to 00b.
31:2
Message Address
RW
If the message enable bit is set, the contents of this register specify the
DWORD aligned address for MSI memory write transaction.
Reset to 0.
7.2.39
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream
Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Message Upper
Address
RW
This register is only effective if the device supports a 64-bit message address
is set.
Reset to 00000000h.
7.2.40
MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Message Data
RW
Reset to 0000h.
7.2.41
VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only)
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