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參數(shù)資料
| 型號(hào)： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 65/77頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開(kāi)關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 68 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
9 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support
boundary scan in PI7C9X20303UL for board-level continuity test and diagnostics. The TAP pins assigned are TCK,
TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins.
9.1
INSTRUCTION REGISTER
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers
including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the
Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to
ensure the machine is in TEST_LOGIC_RESET state at power-up.
PI7C9X20303UL implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined
instruction codes are shown in Table 10-1. Those bit combinations that are not listed are equivalent to the BYPASS
(11111) instruction:
Table 9-1 Instruction register codes
Instruction
Operation Code (binary)
Register Selected
Operation
EXTEST
00000
Boundary Scan
Drives / receives off-chip test data
SAMPLE
00001
Boundary Scan
Samples inputs / pre-loads outputs
HIGHZ
00101
Bypass
Tri-states output and I/O pins except TDO pin
CLAMP
00100
Bypass
Drives pins from boundary-scan register and selects Bypass
register for shifts
IDCODE
01100
Device ID
Accesses the Device ID register, to read manufacturer ID, part
number, and version number
BYPASS
11111
Bypass
Selected Bypass Register
INT_SCAN
00010
Internal Scan
Scan test
MEM_BIST
01010
Memory BIST
Memory BIST test
9.2
BYPASS REGISTER
The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a
bypass instruction is in effect. This allows rapid movement of test data to and from other components on the
board. This path can be selected when no test operation is being performed on the PI7C9X20303UL.
9.3
DEVICE ID REGISTER
This register identifies Pericom as the manufacturer of the device and details the part number and revision
number for the device.
Table 9-2 JTAG device ID register
Bit
Type
Value
Description
31-28
RO
0001
Version number
27-12
RO
1001001000000100
Last 4 digits (hex) of the die part number
11-1
RO
01000111111
Pericom identifier assigned by JEDEC
0
RO
1
Fixed bit equal to 1’b1
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| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404GPANBE | 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays |
| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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