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參數(shù)資料
| 型號(hào)： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 60/77頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 63 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
7.2.93
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h (Upstream
Only)
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Port Arbitration
Capability
RO
It indicates the types of Port Arbitration supported by the VC resource. The
Switch supports Hardware fixed arbitration scheme, e.g., Round Robin,
Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports)
and Time-based WRR with 128 phases (3~4 enabled ports).
Reset to 00001001b.
13:8
Reserved
RO
Reset to 000000b.
14
Advanced Packet
Switching
RO
When set, it indicates the VC resource only supports transaction optimized
for Advanced Packet Switching (AS).
Reset to 0b.
15
Reject Snoop
Transactions
RO
This bit is not applied to PCIe Switch.
Reset to 0b.
22:16
Maximum Time
Slots
RO
It indicates the maximum numbers of time slots (minus one) are allocated for
Isochronous traffic. The default value may be changed by SMBus or auto-
loading from EEPROM.
Reset to 7Fh.
23
Reserved
RO
Reset to 0b.
31:24
Port Arbitration
Table Offset
RO
It indicates the location of the Port Arbitration Table (n) as an offset from the
base address of the Virtual Channel Capability register in the unit of DQWD
(16 bytes).
Reset to 04h for Port Arbitration Table (0).
7.2.94
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h (Upstream
Only)
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
TC/VC Map
RW
This field indicates the TCs that are mapped to the VC resource. Bit locations
within this field correspond to TC values. When the bits in this field are set, it
means that the corresponding TCs are mapped to the VC resource. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to FFh.
15:8
Reserved
RO
Reset to 00h.
16
Load Port Arbitration
Table
RW
When set, the programmed Port Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
19:17
Port Arbitration
Select
RW
This field is used to configure the Port Arbitration by selecting one of the
supported Port Arbitration schemes. The permissible values for the schemes
supported by Switch are 000b and 011b at VC0, other value than these
written into this register will be treated as default.
Reset to 000b.
23:20
Reserved
RO
Reset to 0h.
26:24
VC ID
RO
This field assigns a VC ID to the VC resource.
Reset to 000b.
30:27
Reserved
RO
Reset to 0h.
31
VC Enable
RW
0b: it disables this Virtual Channel
1b: it enables this Virtual Channel
Reset to 1b.
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| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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