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參數(shù)資料
| 型號： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 20/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 27 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
ADDRESS
PCI CFG OFFSET
DESCRIPTION
52h
84h (Port 1)
84h: Bit [3]
80h (Port 1)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 1
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 1
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
53h
84h (Port 1)
84h: Bit [31:24]
Power Management Data for Port 1
Bit [15:8]: read only as Data register
54h
84h (Port 2)
84h: Bit [3]
80h (Port 2)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 2
Bit [0]: No_Soft_Reset
Power Management Capability for Port 2
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
55h
84h (Port 2)
84h: Bit [31:24]
Power Management Data for Port 2
Bit [15:8] – read only as Data register
60h
214h (Port 0)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 0
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
62h
214h (Port 1)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 1
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
64h
214h (Port 2)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 2
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
70h
B0h (Port 0)
B0h – Bit [15:0]
Replay Time-out Counter for Port 0
Bit [15:0]: Relay Time-out Counter
72h
B0h (Port 1)
B0h – Bit [15:0]
Replay Time-out Counter for Port 1
Bit [15:0]: Relay Time-out Counter
74h
B0h (Port 2)
B0h – Bit [15:0]
Replay Time-out Counter for Port 2
Bit [15:0]: Relay Time-out Counter
80h
B0h (Port 0)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 0
Bit [31:16]: Acknowledge Latency Timer
82h
B0h (Port 1)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 1
Bit [31:16]: Acknowledge Latency Timer
84h
B0h (Port 2)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 2
Bit [31:16]: Acknowledge Latency Timer
90h
B4h (Port 0)
B4h: Bit [31:16]
PHY Parameter for Port 0
Bit [31:16]: PHY Parameter
92h
B4h (Port 1)
B4h: Bit [31:16]
PHY Parameter for Port 1
Bit [31:16]: PHY Parameter
94h
B4h (Port 2)
B4h: Bit [31:16]
PHY Parameter for Port 2
Bit [31:16]: PHY Parameter
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404GPANBE | 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays |
| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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