參數(shù)資料
型號(hào)： PIC30F2010
廠商： Microchip Technology Inc.
英文描述： dsPIC High-Performance 16-bit Digital Signal Controller Family Overview
中文描述： dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡(jiǎn)介
文件頁(yè)數(shù)： 13/34頁(yè)
文件大?。?/td> 500K
代理商： PIC30F2010
2001 Microchip Technology Inc.
Advance Information
DS70025D-page 13
dsPIC30F
2.6
PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has programma-
ble VDD and VPP supplies, which allow it to verify pro-
grammed memory at VDD min and VDD max for
maximum reliability when programming requiring this
capability. It has an LCD display for instructions and
error messages, keys to enter commands. Inter-
changeable socket modules all package types.
In stand-alone mode, the PRO MATE II device pro-
grammer can read, verify, or program PICmicro
devices. It can also set code protection in this mode.
Runs under MPLAB
Field upgradable firmware
DOS Command Line interface for production
Host, Safe, and
“
Stand Alone
”
operation
Automatic downloading of object file
SQTP serialization adds unique serial number to
each device programmed
In-Circuit Serial Programming Kit
(sold separately)
Interchangeable socket modules
supports all package options
(sold separately)
3.0
EXCEPTION PROCESSING
The dsPIC has 15 exception sources plus RESET,
which are arbitrated based on a priority scheme.
Exceptions are either RESET, fixed priority non-
maskable traps or user programmable priority inter-
rupts. The exception priority table is shown in Figure 3-
1. The interrupts are enabled, prioritized, and con-
trolled using centralized special function registers.
All interrupt sources can be user assigned to one of 8
priority levels, 0 through 7. Each level is associated
with an interrupt vector as shown in Figure 3-1. Level 6
and 0 represent the highest and lowest maskable prior-
ities respectively. Level 7 interrupts are non-maskable
and are handled slightly differently from all other inter-
rupts.
Certain interrupts have specialized control bits for fea-
tures like edge or level triggered interrupts, interrupt on
change, etc. Control of these features remains within
the peripheral module which generates the interrupt.
3.1
Interrupt Priority
The Interrupt Priority bits for each individual interrupt
are located in bits within the Interrupt Priority Control
registers (INTCON). These bits define the priority level
assigned to a particular interrupt.
Multiple interrupts can be assigned the same priority.
Once in the Interrupt Service Routine (ISR) for a partic-
ular priority level, the interrupt can be determined by
polling the interrupt flag bits.
Each interrupt priority has a corresponding interrupt
vector. When an interrupt is serviced, the PC is loaded
with the interrupt vector that corresponds to the priority
level of that interrupt. There are 8 different interrupt
vectors (see Figure 3-1).
3.1.1
CPU PRIORITY REGISTER
The CPU Priority register is used to indicate the current
priority of all pending interrupts and traps.
The initial (reset) state of the CPU Priority register is
0xFFFF. It contains one bit for each interrupt level 0
through 7 and trap priority level 8 through 14. It also
contains one bit for RESET. When an interrupt or trap
is being serviced, the priority status bit associated with
the interrupt is cleared in this register. This register can
also be used to disable higher priority interrupts than
the one currently being serviced.
The Global Interrupt Enable (GIE) bit will disable all
interrupt levels 0 through 6 when clear. Exceptions
greater than priority level 6 are non-maskable so they
cannot be disabled in software.
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