參數(shù)資料
型號(hào)： PIC30F2010
廠商： Microchip Technology Inc.
英文描述： dsPIC High-Performance 16-bit Digital Signal Controller Family Overview
中文描述： dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡(jiǎn)介
文件頁(yè)數(shù)： 7/34頁(yè)
文件大?。?/td> 500K
代理商： PIC30F2010
2001 Microchip Technology Inc.
Advance Information
DS70025D-page 7
dsPIC30F
1.2
Data Address Space
The core features one program space and two data
spaces. The data spaces can be considered either sep-
arately (for some DSP instructions) or together as one
linear address range (for MCU instructions). The data
spaces are accessed using two Address Generation
Units (AGUs) and separate data paths.
1.2.1
DATA SPACES
The X AGU is used by all instructions and supports all
addressing modes. It also supports modulo and bit
reversed addressing for any instruction (subject to
addressing mode restrictions). The X data path is the
return data path for all single data space access
instructions.
The Y AGU and data path are used in concert with the
X AGU by the MAC class of instructions to provide two
concurrent data read paths. No writes occur across the
Y-bus. This class of instructions dedicate two W regis-
ter pointers, W6 and W7, to always operate through the
Y AGU and address Y data space independently from
X data space. Note that during accumulator write to
Data Space, the data address space is considered
combined X and Y, so the write will occur across the X-
bus. Consequently, it can be to any address irrespec-
tive of where the EA is directed.
The Y AGU only supports post modification addressing
modes associated with the MAC class of instructions. It
also supports modulo addressing for automated circu-
lar buffers. Of course, all other instructions can access
the Y data address space through the X AGU when it is
regarded as part of the composite linear space.
The boundary between the X and Y data spaces is arbi-
trary and is defined by the memory address decode
only (the CPU has no knowledge of the physical loca-
tion of X or Y memory). The boundary is not user pro-
gramable, but may change from variant to varient.
Obviously, to present a linear data space to the MCU
instructions, the address spaces of X and Y data
spaces must be contiguous, but this is not an architec-
tural necessity.
All effective addresses (EA) are 16 bits wide and point
to bytes within the data space to facilitate backward
compatibility with the PIC18C. Consequently, the data
space address range is 64K bytes or 32K words.
1.2.2
DATA SPACE WIDTH
The core data width is 16 bits. All internal registers and
data space memory are organized as 16 bits wide
(some CPU registers are not 16 bits wide). Data space
memory is organized in byte addressable, 16-bit wide
blocks.
1.2.3
DATA ALIGNMENT
To help maintain PIC18C backward compatibility and
improve data space memory usage efficiency, the DSC
Core supports both word and byte operations, by way
of an instruction attribute. Data is aligned in data mem-
ory and registers as words, but all data space EAs
resolve to bytes (see Figure 1-4). Data byte reads will
read the complete word which contains the byte, using
the LS-bit of any EA to determine which byte to select.
The selected byte is placed onto the LS-byte of the X
data path (no byte accesses are possible from the Y
data path as the MAC class of instruction can only fetch
words). That is, data memory and registers are orga-
nized as two parallel byte wide entities with shared
(word) address decode but separate write lines. Data
byte writes will only write to the corresponding side of
the array or register which matches the byte address.
For word accesses, the LS-bit of the EA is ignored
(don
’
t care).
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations which are restricted to word size) are
automatically scaled to step through word aligned
memory. For example, the core recognizes that post
modified register indirect addressing mode, [Ws]+=1,
will result in a value of Ws+1 for byte operations and
Ws+2 for word operations.
All word accesses must be aligned (to an even
address). Misaligned word data fetches are not sup-
ported, so care must therefore be taken when mixing
byte and word operations or translating from PIC18C
code. Should a misaligned read or write be attempted,
an address fault trap will be forced.
FIGURE 1-4:
DATA ALIGNMENT
All byte loads into any W register are loaded into the
LS-byte. The MS-byte is not modified.
Note:
Byte operations use the 16-bit ALU and can
produce results in excess of 8 bits. How-
ever, to maintain PIC18C backwards com-
patibility, the ALU result from all byte
operations is written back as a byte (i.e.,
MS byte not modified), and the status regis-
ter is updated based only upon the state of
the LS-byte of the result.
15
8 7
0
0001
0003
0005
0000
0002
0004
Byte1 Byte 0
Byte3 Byte 2
Byte5 Byte 4
LS byte
MS byte
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