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參數(shù)資料
| 型號： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數(shù)字信號的高性能16位數(shù)字信號控制器系列簡介 |
| 文件頁數(shù)： | 21/34頁 |
| 文件大小： | 500K |
| 代理商： | PIC30F2010 |
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2001 Microchip Technology Inc.
Advance Information
DS70025D-page 21
dsPIC30F
6.3
Watchdog Timer Module
This is the description of Watchdog Timer (WDT) for the
dsPIC30F family.
6.3.1
OVERVIEW
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software mal-
function. The WDT is a free running timer which runs off
an on-chip RC oscillator, requiring no external compo-
nent. Therefore, the WDT timer will continue to operate
even if the main processor clock (e.g., the crystal oscil-
lator) fails.
6.3.2
ENABLING AND DISABLING THE
WDT
The Watchdog timer can be
“
Enabled
”
or
“
Disabled
”
only through a configuration bit (WDTEN) in the Config-
uration Register.
WDTEN=1 enables the Watchdog timer. The enabling
is done when programming the device. By default, after
chip-erase, WDTEN bit =1. Any device programmer
capable of programming dsPIC devices (such as
Microchip
’
s PRO MATE
II and PICSTART
Plus pro-
grammers) allows programming of this and other con-
figuration bits to the desired state.
If enabled, the WDT will increment until it overflows or
“
times out
”
. A WDT time-out will force a device reset
(except during SLEEP). To prevent a WDT time-out,
the user must clear the Watchdog timer using a CLR-
WDT instruction.
If a WDT times out during SLEEP, the device will wake
up. The status bit will be cleared (
“
0
”
) to indicate a
Wake-up resulting from WDT time-out
6.4
Motor Control PWM Module
This module simplifies the task of generating multiple,
synchronized pulse width modulated (PWM) outputs. In
particular, the following power and motion control appli-
cations are supported by the PWM module:
Three-Phase AC Induction Motor
Switched Reluctance (SR) Motor
Brushless DC (BLDC) Motor
Uninterruptable Power Supply (UPS)
6.4.1
FEATURES OVERVIEW
The PWM module has the following features:
Up to 8 PWM I/O pins with 4 duty cycle genera-
tors
Up to 16-bit resolution
‘
On-the-Fly
’
PWM frequency changes
Edge and center aligned output modes
Single-pulse generation mode
Interrupt support for asymmetrical updates in cen-
ter-aligned mode.
Output override control for electrically commu-
tated motor (ECM) operation
‘
Special Event
’
comparator for scheduling other
peripheral events
A simplified block diagram of the PWM module is
shown in Figure 6-4.
This module contains 4 duty cycle generators, num-
bered 1 through 4. The module has 8 PWM output pins,
numbered 0 through 7. The eight I/O pins are grouped
into odd numbered/even numbered pairs. For comple-
mentary loads, the even PWM pins must always be the
complement of the corresponding odd I/O pin to pre-
vent damage to the power transistor devices. Conse-
quently, the signals on the even numbered I/O pins
have certain limitations when the module is in the com-
plementary operating mode.
6.4.2
PWM TIMEBASE
The PWM timebase is provided by a 16-bit timer with a
prescaler and postscaler. The PWM timebase is config-
ured via a special function register (SFR).
The PWM timebase can be configured for four different
modes of operation:
Free running mode
Single-shot mode
Continuous up/down count mode
Continuous up/down count mode with interrupts
for double-updates.
These
four
modes
are
PTMOD1:PTMOD0 bits in the PTCON SFR. The up/
down counting modes support center-aligned PWM
generation. The single-shot mode allows the PWM
module to support pulse control of certain electronically
commutated motors (ECMs).
selected
by
the
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