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參數(shù)資料
| 型號(hào)： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡介 |
| 文件頁數(shù)： | 15/34頁 |
| 文件大?。?/td> | 500K |
| 代理商： | PIC30F2010 |
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2001 Microchip Technology Inc.
Advance Information
DS70025D-page 15
dsPIC30F
3.2.1.1
RESET Sources
In addition to external and power-on resets, there are
three sources of error conditions which will
‘
trap
’
to the
reset vector. The possibility of recovery from these con-
ditions is remote, so a hardware reset is the most
robust course of action.
Watchdog Time-out:
The windowed watchdog has been reset too early
or has timed out, indicating that the processor is
no longer executing the correct flow of code.
Illegal Instruction Trap:
The dsPIC 8-bit opcode field must be fully
decoded. Attempted execution of any unused
slots will result in an illegal instruction trap. Note
that a fetch of an illegal instruction will not result in
an illegal instruction trap if that instruction is
flushed prior to execution due to a flow change.
Brown-out Detect:
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
3.2.1.2
The following traps are provided with increasing prior-
ity. However, as all traps are nestable, priority has little
effect.
Software trap:
Execution of a TRAP opcode will cause an inter-
rupt.
Arithmetic Error trap:
The Arithmetic Error trap will execute under the
following three circumstances. It is assumed that
the DSP engine configuration will be consistent
within an application, so polling flags to determine
the error condition should not be necessary.
1.
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
2.
If enabled, an Arithmetic Error trap will be taken
when an arithmetic operation on either accumu-
lator A or B causes an overflow from bit 31 and
the accumulator guard bits are unutilized.
3.
If enabled, an Arithmetic Error trap will be taken
when an arithmetic operation on either accumu-
lator A or B causes a catastrophic overflow from
bit 39 and all saturation is disabled.
Address Error Trap:
This trap will be initiated when any of the following
circumstances occurs:
1.
A misaligned data word fetch is attempted
2.
A data fetch from unimplemented data address
space is attempted
3.
A program fetch from unimplemented user pro-
gram address space is attempted
4.
A program fetch from vector address space is
attempted
TRAP Sources
5.
A read (for address) of an uninitialized W regis-
ter is attempted.
Stack Error Trap
This trap will be initiated under the following con-
ditions:
1.
The stack pointer is loaded with a value which is
greater than the (user programmable) limit value
written into the SPLIM register (stack overflow).
2.
The stack pointer is loaded with a value which is
less than 0x0200 (simple stack underflow).
Oscillator Fail Trap:
This trap will be initiated should the external oscil-
lator fail and operation become reliant on an inter-
nal RC backup.
It is conceivable that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 3-1 will be implemented
which may require the user to check if other traps are
pending in order to completely correct the fault.
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