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參數(shù)資料
| 型號(hào)： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡介 |
| 文件頁數(shù)： | 26/34頁 |
| 文件大?。?/td> | 500K |
| 代理商： | PIC30F2010 |
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dsPIC30F
DS70025D-page 26
Advance Information
2001 Microchip Technology Inc.
6.8
SPI
Module
6.8.1
OPERATING FUNCTION
DESCRIPTION
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices may be Serial EEPROMs, shift reg-
isters, display drivers, A/D converters, etc.
This SPI module includes all SPI modes. A Frame Syn-
chronization mode is also included for support of voice
band CODECs. The following sections describe the
basic functionality of the SPI module. Figure 6-8 shows
a block diagram of the SPI.
6.8.2
SERIAL PERIPHERAL INTERFACE
(SPI)
SPI mode is a high-speed serial I/O interface useful for
communicating with peripheral devices (e.g., serial
EEPROM, serial A/D) and for I/O expansion. It is com-
patible with Motorola
’
s SPI
and SIOP interfaces.
The serial port consists of a 16-bit shift register, SPISR,
used for shifting data in and out, and a buffer register,
SPIBUF. A control register, SPICON, configures the
module. Additionally, a status register, SPISTAT, indi-
cates various status conditions. Five pins make up the
serial interface; SDI: serial data input; SDO: serial data
output; SCK: shift clock input or output, SS: active low
slave select and FSYNC: frame synchronization pulse.
In master mode operation, SCK is clock output, but in
slave mode, it is clock input.
The control bit SPIEN along with several control bits
enables the serial port and configures SDI, SDO, SCK
and SS pins as serial port pins.
A series of eight clock pulses shift out 8 bits from the
SPISR to SDO pin and simultaneously shift in 8-bit data
from SDI pin. An interrupt is generated when the trans-
fer is complete (interrupt flag bit SPIIF). This interrupt
can be disabled through the interrupt enable bit SPIIE.
The receive operation is double buffered. When a com-
plete byte is received it is transferred from SPISR to
SPIBUF.
Transmit operation is not double buffered. The user
writes directly to SPISR. Whereas a read operation will
read SPIBUF, a write operation will write to both SPISR
and SPIBUF.
In master mode, the clock is generated by prescaling
the system clock. When an external clock source is
used, a minimum high and low time must be observed.
In master mode, data is transmitted as soon as
SPIBUF is written. The interrupt is raised at the middle
of the last bit duration (i.e., after the last bit in is
latched).
In slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the inter-
rupt is set as the last bit is latched in. If SS control is
enabled, then transmission and reception are enabled
only when SS = low. SDO output will be disabled in SS
mode with SS = high.
6.8.3
DIRECTION CONTROL OF SPI PINS
The input/output direction control on all the SPI pins is
controlled by the SPI module. Therefore, control sig-
nals generated within the module will override the data
direction control register on each SPI pin based on the
current operating mode of the module.
The SPI module can give up control of three pins. The
SS pin is only controlled in slave mode with SS
enabled. SDO has a control bit in SPICON that allows
the module to disable direction control, DISSDO.
FSYNC pin is only controlled when the FRMEN bit is
high.
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