參數(shù)資料
型號(hào)： PIC30F2010
廠商： Microchip Technology Inc.
英文描述： dsPIC High-Performance 16-bit Digital Signal Controller Family Overview
中文描述： dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡(jiǎn)介
文件頁(yè)數(shù)： 29/34頁(yè)
文件大小： 500K
代理商： PIC30F2010
2001 Microchip Technology Inc.
Advance Information
DS70025D-page 29
dsPIC30F
FIGURE 6-9:
I
2
C BLOCK DIAGRAM (I
2
C RECEIVE)
FIGURE 6-10:
I
2
C BLOCK DIAGRAM (I
2
C TRANSMIT)
6.10.5
PIN CONFIGURATION IN I
2
C MODE
In I
2
C mode, pin SCL is clock and pin SDA is data. The
module will override the data direction bits for these
pins. The pins that are used for I
2
C modes are config-
ured as open-drain.
6.10.6
I
2
C REGISTERS
I2CCON, and I2CSTAT are control and status registers,
respectively. The I2CCON registers is readable and
writable. The lower 6 bits of the I2CSTAT are read-only.
The remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data in
Figure 6-9.
I2CRCV is the buffer register to which data bytes are
written to or read from. This register is the receive
buffer, as shown in Figure 6-9. I2CXMT is the transmit
register; bytes are written to this register during a trans-
mit operation, as shown in Figure 6-10.
I2CADD register holds the slave address, and this reg-
ister is now 10 bits wide to hold the full slave address.
If 10-bit mode is desired, the 10-bit address preamble
is recognized by the module, which then automatically
enables 10-bit addressing mode. A status bit, ADD10,
indicates 10-bit address mode. The I2CBRG acts as
the baud rate generator reload value. The baud rate
generator is a full baud rate generator.
In receive operations, I2CRSR and I2CRCV together
create a double buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and the i2c_int_flag interrupt is set. During transmis-
sion, the I2CTRN is not double buffered.
Acknowledge
Generation
Read
Write
I2CRSR
I2CRCV
Internal
data bus
MSB
SCL
SDA
Shift
clock
Match detect
I2CADD
Start and
Stop bit detect
Set, Reset
S, P bits
(I2CSTAT Reg)
Addr_Match
Read
Write
I2CTRN
Internal
data bus
MSB
SCL
SDA
Shift
clock
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