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參數(shù)資料
| 型號： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數(shù)字信號的高性能16位數(shù)字信號控制器系列簡介 |
| 文件頁數(shù)： | 25/34頁 |
| 文件大?。?/td> | 500K |
| 代理商： | PIC30F2010 |
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2001 Microchip Technology Inc.
Advance Information
DS70025D-page 25
dsPIC30F
6.7
Output Compare/ PWM module
This is a description of the Output Compare module
and associated operational modes. The Output Com-
pare module features are quite useful in applications
requiring operational modes such as:
Generation of variable width output pulses
Power Factor Correction
Simple PWM Operation
The following section provides a basic description of
the Output Compare/PWM module. Table 6-2 presents
the timer resource allocation.
TABLE 6-2:
OUTPUT COMPARE
SUGGESTED TIMER
RESOURCE
6.7.1
OUTPUT COMPARE MODULARITY
The Output Compare module consists of 1 to
“
N
”
output
compare channels with the following feature enhance-
ments. The key operational features are, but not limited
to:
Timer2 and Timer3 selection mode
Simple Output Compare match mode
Dual Output Compare match mode
Simple glitchless PWM mode
Output Compare during sleep mode
Interrupt on output compare/PWM event
These operating modes are determined by setting the
appropriate bits in Output Compare SFR (Special
Function Register). Figure 6-7 depicts the output com-
pare mode block diagram.
CMPRxM and CMPRxS in the figure represent the dual
compare registers. In the dual compare mode, the
CMPRxS register is used for the first compare and
CMPRxM is used for the second compare. When con-
figured for the PWM mode of operation, the CMPRxS
is the slave latch (read-only) and CMPRxM is the mas-
ter latch.
FIGURE 6-7:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Functional Mode
Timer Resource
Output Compare 1 - N
Timer 2 or Timer 3
CMPRxS
Comparator
OutPut
Logic
Q
S
R
CMPxM2:CMPxM0
Mode Select
Output Enable
OCx/PWMx
Set Flag Bit
CMPxIF
CMPRxM
3
Note 1:
Where
‘
x
’
is shown reference is made to the registers associated to the respective output com-
pare channels 1, 2, 3 or 4.
0
1
PWMFLT
OCxTSEL
0
1
T2P2_MATCH
T2<15:0> T3<15:0>
T3P3_MATCH
From GP Timer Module
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