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參數(shù)資料
| 型號(hào)： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡介 |
| 文件頁數(shù)： | 3/34頁 |
| 文件大?。?/td> | 500K |
| 代理商： | PIC30F2010 |
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2001 Microchip Technology Inc.
Advance Information
DS70025D-page 3
dsPIC30F
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high speed 16-bit by 16-bit multiplier, a 40-
bit ALU, two 40-bit saturating accumulators and a 40-
bit bi-directional barrel shifter. The barrel shifter is
capable of shifting a 40-bit value up to 15 bits right or
up to 16 bits left in a single cycle. The DSP instructions
operate seamlessly with all other instructions and have
been designed for optimal real-time performance. The
MAC class of instructions can concurrently fetch two
data operands from memory while multiplying two W
registers and accumulating the results. This requires
that the data space be split for these instructions and
linear for all others. This is achieved in a transparent
and flexible manner through dedicating certain working
registers to each address space for the MAC class of
instructions.
The core features a sophisticated interrupt structure
with 15 individually prioritized vectors. The interrupts
and exceptions consist of reset, 7 traps and 8 inter-
rupts. Up to 32 interrupt sources are supported. One
interrupt level may be selected (typically the highest
one) to execute as a fast (1 cycle entry, 1 cycle exit)
interrupt. This function is actually an extension of the
logic required to allow a REPEAT instruction loop to be
interrupted, which can significantly reduce latency in
some application.
A block diagram of the core is shown in Figure 1-1.
1.1.1
COMPILER DRIVEN
ENHANCEMENTS
In addition to DSP performance requirements, the core
architecture was strongly influenced by recommenda-
tions which would lead to a more efficient (code size
and speed) C compiler.
1.
For most instructions, the core is capable of exe-
cuting a data (or program data) memory read, a
working register (data) read, a data memory
write and a program (instruction) memory read
per instruction cycle. As a result, 3 operand
instructions can be supported, allowing A+B=C
operations to be executed in a single cycle.
2.
Instruction addressing modes are extremely
flexible to meet compiler needs.
3.
The working register array is comprised of 16 x
16-bit registers, each of which can act as data,
address or offset registers. One working register
(W15) operates as the software stack pointer for
interrupts and calls.
4.
Linear indirect access of all data space is possi-
ble, plus the memory direct address range has
been extended to 8K bytes. This, together with
the addition of 16-bit direct address LOAD and
STORE instructions, has provided a contiguous
linear addressing space.
5.
Linear indirect access of 32K word (64K byte)
pages within program space is possible using
any working register via new table read and
write instructions.
Part of data space can be mapped into program
space, allowing constant data to be accessed as
if it were in data space.
6.
1.1.2
INSTRUCTION FETCH MECHANISM
A one-stage pre-fetching mechanism accesses each
instruction a cycle ahead to maximize available execu-
tion time. Most instructions execute in a single cycle.
Exceptions are:
1.
Flow control instructions (such as program
Branches, Calls, Returns) take 2 cycles since
the IR (instruction register) and pre-fetch buffer
must be flushed and refilled.
2.
Instructions where one operand is to be fetched
from program space (using any method). These
operations consume 2 cycles (with the notable
exception of the MAC class of DSP instructions
executed within a REPEAT loop which executes
in 1 cycle).
Most instructions access data as required during
instruction execution. Instructions which utilize the mul-
tiplier array must have data available at the beginning
of the instruction cycle. Consequently, this data must
be prefetched, usually by the preceding instruction,
resulting in a simple out of order data processing
model.
A programmer model diagram is shown in Figure 1-2.
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