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參數(shù)資料
| 型號： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數(shù)字信號的高性能16位數(shù)字信號控制器系列簡介 |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 500K |
| 代理商： | PIC30F2010 |
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dsPIC30F
DS70025D-page 14
Advance Information
2001 Microchip Technology Inc.
3.2
Exception Sequence
All interrupt event flags are sampled simultaneously
and at a specific CPU clock phase. A pending interrupt
indicated by the flag bit being equal to a
‘
1
’
will cause
the interrupt to occur. When an interrupt is latched, the
interrupt priority bits associated with a pending flag are
sampled in the next clock cycle before entering the
ISR.
The sampling sequence is needed to determine if more
than one interrupt flag, with different priorities, have
been simultaneously latched. Each of the interrupt sta-
tus bits is arbitrated simultaneously.
Each of the pending interrupts has an associated prior-
ity. The status of the pending interrupt is presented on
one bit of an 8-bit Interrupt Request (IRQ) bus corre-
sponding to one of 8 priorities. Each bit on the request
bus indicates to the CPU that at least one interrupt of
priority
‘
n
’
is present.
If the IRQ bits sampled indicate a priority lower than or
equal to the current CPU priority, then no interrupt
sequence will occur. When all higher (priority) status
bits are set as a result of the termination of their respec-
tive ISR
’
s, then the ISR of the pending status bit will be
serviced.
When an interrupt is serviced, the return address is
pushed onto the stack together with the least significant
byte of the Status Register (SR) as shown in Figure 3-1.
Working Register 15 is used as the implied stack pointer.
FIGURE 3-1:
0x0000
INTERRUPT STACK FRAME
If interrupt nesting is disabled, subsequent interrupts of
priority level 0 through 6 are prevented from causing a
further exception sequence. However, interrupts con-
tinue to be arbitrated and the CPU Priority register con-
tinues to be updated to reflect all subsequent interrupts
which become pending. Individual interrupt flag bits
within the IFS (Interrupt Flag Status) register(s) are set
regardless of the status of the GIE and the individual
Interrupt Priority bits. The GIE bit is also cleared on
RESET. Note that traps and priority 7 interrupts are not
disabled by the GIE bit and are always enabled.
If interrupt nesting is enabled, subsequent interrupts
will be arbitrated and will clear the CPU Priority register
bits accordingly. Should any of these be of a higher pri-
ority than that currently being serviced, an interrupt at
that level will be initiated.
Note:
Traps and priority 7 interrupts are always
nestable.
3.2.1
INTERRUPT/TRAP/RESET
VECTORS
Interrupt, trap and reset vectors are automatically
loaded into the PC when servicing an interrupt, trap or
following a RESET. The vectors are contained in loca-
tions 0x000000 through 0x00001F of program memory.
These locations contain 24-bit addresses, and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random data.
TABLE 3-1:
EXCEPTION VECTOR TABLE
Traps can be considered as non-maskable, nestable
interrupts which adhere to a predefined priority as
shown in Table 3-1. They are intended to provide the
user a means to correct erroneous operation during
debug and when operating within the application. The
software traps also provide a means to emulate new or
unsupported instructions.
Note:
If the user does not intend to take corrective
action in the event of a trap error condition,
these vectors must be loaded with the reset
vector address.
Note that many of these trap conditions can only be
detected when they happen. Consequently, the ques-
tionable instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action which
caused the trap may therefore have to be corrected.
<Free Word>
PC[15:0]
SR[7:0]:PC[23:16]
0
15
W15 (before CALL)
W15 (after CALL)
S
H
PUSH : [W15]+=2
POP : [W15-=2]
Reset Vector
Ext. Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Arithmetic Warning Trap Vector
Software Trap Vector
Reserved Vector
Reserved Vector
Priority 7 Interrupt Vector
Priority 6 Interrupt Vector
Priority 5 Interrupt Vector
Priority 4 Interrupt Vector
Priority 3 Interrupt Vector
Priority 2 Interrupt Vector
Priority 1 Interrupt Vector
Priority 0 Interrupt Vector
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