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參數(shù)資料
| 型號(hào)： | PIC30F2010 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | dsPIC High-Performance 16-bit Digital Signal Controller Family Overview |
| 中文描述： | dsPIC數(shù)字信號(hào)的高性能16位數(shù)字信號(hào)控制器系列簡(jiǎn)介 |
| 文件頁數(shù)： | 32/34頁 |
| 文件大?。?/td> | 500K |
| 代理商： | PIC30F2010 |
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dsPIC30F
DS70025D-page 32
Advance Information
2001 Microchip Technology Inc.
6.12
I/O Pins
Some pins for the I/O pin functions are multiplexed with
an alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
All I/O port pins have three registers directly associated
with the operation of the port pin. The Data Direction
Register determines whether the pin is an input or an
output. The port Data Latch Register provides latched
output data for the I/O pins. The Port Register provides
visibility of the logic state of the I/O pins. Reading the
Port Register provides the I/O pin logic state, while
writes to the Port Register write the data to the port
Data Latch Register. Figure 6-12 illustrates a PORT/
LAT/TRIS block diagram.
FIGURE 6-12: SIMPLIFIED BLOCK
DIAGRAM OF PORT/LAT/TRIS
OPERATION
6.12.1
I/O PIN FEATURES
Schmitt Trigger input
Open drain output.
TTL input levels
CMOS output drivers
Weak internal pull-up (gated)
Interrupt on change feature (inputs only)
6.12.2
I/0 Port Latch
Some I/O port pins have latch bits (LATCH register).
The LATCH register when read will yield the contents of
the I/O latch, and when written will modify the contents
of the I/O latch, thus modifying the value driven out on
a pin if the corresponding Data Direction Register bit is
configured for output. This can be used in read-modify-
write instructions that allow the user to modify the con-
tents of the latch register regardless of the status of the
corresponding pins.
Q
D
CK
WR LAT +
WR PORT
Data Latch
I/O pin
RD PORT
TRIS
RD LAT
Data Bus
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