參數(shù)資料
型號: PM73488
廠商: PMC-SIERRA INC
元件分類: 數(shù)字傳輸電路
英文描述: 5 Gbit/s ATM Switch Fabric Element
中文描述: ATM SWITCHING CIRCUIT, PBGA596
封裝: EPBGA-596
文件頁數(shù): 111/135頁
文件大小: 1735K
代理商: PM73488
PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
113
Figure 43. TAP Controller Finite State Machine
10.2.1
Test-Logic-Reset:
The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The
state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of
the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the
Test-Logic-Reset
Run-Test-Idle
Select-DR-Scan
Select-IR-Scan
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
TRSTB=0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
All transitions dependent on input TMS
0
0
0
0
0
1
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