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參數(shù)資料
| 型號： | PM73488 |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 5 Gbit/s ATM Switch Fabric Element |
| 中文描述： | ATM SWITCHING CIRCUIT, PBGA596 |
| 封裝： | EPBGA-596 |
| 文件頁數(shù)： | 42/135頁 |
| 文件大?。?/td> | 1735K |
| 代理商： | PM73488 |
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PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
44
If the cell was blocked at an output of the QSE because the entire gang is disabled (the default is ACK), then
the cell is to be cleared when all ports to a QRT are known to be unavailable.
If the cell was successfully routed through the QSE, the return path is set up to route the data-acknowledge
signal back from the next switch stage.
For multicast traffic, the BP_ACK_IN and BP_ACK_OUT signals also serve as a backpressure signal, indicating at
each cell time, the multicast cell priority the QSE can accept on the following cell time on a given port.
3.3
The QSE has a non-multiplexed, asynchronous, general-purpose microprocessor interface (PIF) through which the
internal registers can be accessed. The external SSRAM is also indirectly accessed through this same interface.
Microprocessor Interface
3.4
The QSE supports 128 internal multicast groups, and is expandable up to 256K through an external SSRAM.
Multicast SRAM Interface
3.5
The QSE is driven from a single clock source up to a maximum clock rate of 66 MHz.
Clocks and Timing Signals
To indicate the SOC, there is one SE_SOC_IN signal per input port. There is one SE_SOC_OUT signal per group of
four outputs.
Cells must arrive at the input ports within an eight clock-cycle window. A CELL_START is used as a reference for
an internal cell start signal to determine the eight clock-cycle window in which the SOC signal on the SE_SOC_IN
lines are valid. The internal cell start signal delay from the external CELL_START signal is programmed in the
CELL_START_OFFSET (refer to
section 9.3.28 “CELL_START_OFFSET” on page 109
).
3.6
CTRL_IN is a one bit input port. Its function depends on the value of the
“ENABLE_STAT_PINS” (bit 7) bit in the
CHIP_MODE register. When this bit is “0”, CTRL_IN directly sets the value of the internal “No Data Out” control bit.
What this internal bit does is explained later. When this bit is “1”, CTRL_IN expects a data packet which sets the value of
both, the internal “/No Data Out” and the “/No Data In” registers.
CTRL_IN
The format for the data packet is described below:
Data on this line has to be clocked out by its source at one-eighth the QSE clock rate. CTRL_IN is normally “0”. A
valid data packet starts with a “0” -> “1” transition on the line (implying that the first “bit” of the data packet is “1”).
A valid data packet starts with “100
b
” followed by 2 control bits and 6 bits which are ignored. If the first 3 bits of a
data packet are not “100
b
”, the data packet is ignored (i.e. the next 8 bits are ignored). Data packets may not arrive
back to back. At least 4 zero bits must be present between any two data packets.
A valid data packet is therefore: “100b
0
b
1
XXXXXX
b
”. b
0
is the desired value of “/No Data In” and b
1
is the desired
value of “/No Data Out”.
If the internal “/No Data In” bit is asserted the QSE will continously apply back pressure on all inputs and all priori-
ties. If the internal “/No Data Out” bit is asserted the QSE will behave as if all its outputs are receiving backpressure
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