![](http://datasheet.mmic.net.cn/330000/PM8315_datasheet_16444435/PM8315_187.png)
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
172
manipulate the outputs of the block and consequently the device outputs
(refer to the "Test Mode 0 Details" in the "Test Features" section).
HIZIO:
The HIZIO bit controls the tri-state modes of the output pins of the TEMUX.
While the HIZIO bit is a logic 1, all output pins of the TEMUX, except the data
bus, are held in a high-impedance state. The microprocessor interface is still
active.
HIZDATA:
The HIZDATA bit controls the tri-state modes of the TEMUX. While the HIZIO
bit is a logic 1, all output pins of the TEMUX, except the data bus, are held in
a high-impedance state. While the HIZDATA bit is a logic 1, the data bus is
also held in a high-impedance state which inhibits microprocessor read
cycles.
11.1 JTAG Test Port
The TEMUX JTAG Test Access Port (TAP) allows access to the TAP controller
and the 4 TAP registers: instruction, bypass, device identification and boundary
scan. Using the TAP, device input logic levels can be read, device outputs can
be forced, the device can be identified and the device scan path can be
bypassed. For more details on the JTAG port, please refer to the Operations
section.
Table 11
- Instruction Register
Length - 3 bits
Instructions
Selected Register
Instruction Code IR[2:0]
EXTEST
Boundary Scan
000
IDCODE
Identification
001
SAMPLE
Boundary Scan
010
BYPASS
Bypass
011
BYPASS
Bypass
100
STCTEST
Boundary Scan
101
BYPASS
Bypass
110
BYPASS
Bypass
111