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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
48
Pin Name
Type
Pin
No.
Function
CMVFPB
Input
M2
Common MVIP Frame Pulse (CMVFPB).
The active
low common frame pulse for 8.192 Mbps H-MVIP
signals references the beginning of each frame for links
operating in 8.192Mbps H-MVIP mode.
The H-MVIP interfaces are enabled via the
SYSOPT[2:0] bits in the Global Configuration register.
The CMVFPB frame pulse occurs every 125us for a
and is sampled on the falling edge of CMVFPC.
This signal shares a pin with CEFP. By default this input
is CEFP.
MVID[1]
MVID[2]
MVID[3]
MVID[4]
MVID[5]
MVID[6]
MVID[7]
Output AA5
R19
Y2
P21
U2
M19
J1
H-MVIP Ingress Data (MVID[1:7]).
MVID[x] carries the
recovered T1 or E1 channels which have passed
through the elastic store. Each MVID[x] signal carries
the channels of four complete T1s or E1s. MVID[x]
carries the T1 or E1 data equivalent to ID[(4x-3):(4x)].
MVID[x] is aligned to the common H-MVIP 16.384Mb/s
clock, CMV8MCLK, frame pulse clock, CMVFPC, and
frame pulse, CMVFPB. MVID[x] is updated on every
second rising or falling edge of the common H-MVIP
16.384Mb /s clock, CMV8MCLK, as fixed by the
common MVIP frame pulse clock, CMVFPC. The
updating edge of CMV8MCLK is selected via the
CMVIDE bit in the Master Common Ingress Serial and
H-MVIP Interface Configuration register.
In E1 mode only MVID[1:6] are used.
MVID[1:7] shares the same pins as
ID[1,5,9,13,17,21,25].