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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
65
ALE
Input
D17
Address Latch Enable (ALE).
This signal is active
high and latches the address bus A[13:0] when low.
When ALE is high, the internal address latches are
transparent. It allows the TEMUX to interface to a
multiplexed address/data bus. The ALE input has an
integral pull up resistor.
JTAG Interface
TCK
Input
C3
Test Clock (TCK).
This signal provides timing for test
operations that can be carried out using the IEEE
P1149.1 test access port.
TMS
Input
C2
Test Mode Select (TMS).
This signal controls the test
operations that can be carried out using the IEEE
P1149.1 test access port. TMS is sampled on the rising
edge of TCK. TMS has an integral pull up resistor.
TDI
Input
C4
Test Data Input (TDI).
This signal carries test data into
the TEMUX via the IEEE P1149.1 test access port. TDI
is sampled on the rising edge of TCK. TDI has an
integral pull up resistor.
TDO
Output B3
Test Data Output (TDO).
This signal carries test data
out of the TEMUX via the IEEE P1149.1 test access
port. TDO is updated on the falling edge of TCK. TDO
is a tri-state output which is inactive except when
scanning of data is in progress.
TRSTB
Input
B1
Active low Test Reset (TRSTB).
This signal provides
an asynchronous TEMUX test access port reset via the
IEEE P1149.1 test access port. TRSTB is a Schmitt
triggered input with an integral pull up resistor. TRSTB
must be asserted during the power up sequence.
Note that if not used, TRSTB must be connected to the
RSTB input.
Miscellaneous Pins
TEMUXSELB
Input
AA2
TEMUX Mode Select (TEMUXSELB).
The TEMUX
Mode Select pin is used for internal testing and must be
connected to ground for proper operation.
TEMUXSELB has an integral pull up resistor
NO CONNECT
A1
B2
No Connect.
These pins are not connected to any
internal logic.