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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
266
register. The values of the don’t-care bits are not important, except that they will
be used in the backplane parity check if it is enabled.
Figure 81
- T1 Egress Interface 2.048 MHz Clock Slave: External
Signaling Mode
ED[x]
ESIG[x]
Ch24
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch23
Ch24
Ch1
CECLK
CEFP
ED[x]
ESIG[x]
A B C D
Channel 1
A B C D
Channel 2
1 2 3 4 5 6 7 8
A B C D
Channel 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Don't Care
Don't Care
A B C D
Channel 4
1 2 3 4 5 6 7 8
Don't Care
Don't Care
"filler"
CECLK
CEFP
F-Bit or
Parity
F
The Egress Interface is configured for the 2.048 MHz Clock Slave: External
Signaling Mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface
Mode Select register. The 2.048 MHz internally gapped clock mode is selected
by writing CECLK2M to logic 1 in the Master Egress Slave Mode Serial Interface
register. In the illustrated case, CEFP specifies frame alignment and is required
to pulse high for one cycle every frame. ESIG[x] should carry the signaling bits
for each channel in bits 5,6,7 and 8; the signaling bits will be inserted into the
data stream by the transmitter. If parity checking is enabled, a parity bit should
be inserted on ED[x] and ESIG[x] in the first bit of each frame. The values of the
don’t-care bits are not important, except that they will be used in the backplane
parity check if it is enabled.
Figure 82
- T1 and E1 Egress Interface Clock Slave: Clear Channel Mode
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ECLK[x]
ED[x]
8