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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
43
Pin Name
Type
Pin
No.
Function
CTCLK
Input
M3
Common Transmit Clock (CTCLK).
This input signal
is used as a reference transmit tributary clock which
can be used in egress Clock Master modes.
Depending on the configuration of the TEMUX, CTCLK
may be a line rate clock (so the transmit clock is
generated directly from CTCLK, or from CTCLK after
jitter attenuation), or a multiple of 8kHz (Nx8khz, where
1
≤
N
≤
256) so long as CTCLK is jitter-free when divided
down to 8kHz (in which case the transmit clock is
derived by the DJAT PLL using CTCLK as a
reference).
The TEMUX may be configured to ignore the CTCLK
input and utilize CECLK or one of the recovered
Ingress clocks instead, RECVCLK1 and RECVCLK2.
Receive tributary clock[x] is automatically substituted
for CTCLK if line loopback is enabled.
CECLK
Input
N4
Common Egress Clock (CECLK).
The common
egress clock is used to time the egress interface when
Clock Slave mode is enabled in the egress side.
CECLK may be a 1.544MHz or 2.048MHz clock with
optional gapping for adaptation from non-uniform
system clocks. When the Clock Slave: EFP Enabled
mode is active, CEFP and ED[x] are sampled on the
active edge of CECLK, and EFP[x] is updated on the
active edge of CECLK. When the Clock Slave:
External Signaling mode is active, CEFP, ESIG[x] and
ED[x] are sampled on the active edge of CECLK.
CECLK is a nominal 1.544 or 2.048 MHz clock +/-
50ppm with a 50% duty cycle.
This signal shares a pin with the H-MVIP signal
CMV8MCLK. By default this input is CECLK.