![](http://datasheet.mmic.net.cn/330000/PM8315_datasheet_16444435/PM8315_278.png)
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
263
Figure 75
- T1 and E1 Egress Interface Clock Master: Clear Channel
Mode
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ECLK[x]
ED[x]
8
The Egress Interface is configured for the Clock Master: Clear Channel mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
ED[x] is sampled on the rising edge of the ECLK[x] output. When the the EDE bit
in the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is
sampled on the falling edge of ECLK[x], and the functional timing is described by
Figure 75 with the ECLK[x] signal inverted.
Figure 76
- T1 Egress Interface Clock Slave: EFP Enabled mode
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8
Channel 24
F-bit or Parity
Channel 1
Channel 2
Channel 24
F-bit or Parity
Channel 1
CECLK
CEFP
ED[x]
EFP[x]
Figure 77
- E1 Egress Interface Clock Slave : EFP Enabled Mode
Timeslot 0
Timeslot 1
Timeslot 0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Timeslot 31
Parity bit
(if enabled)
Timeslot 31
Parity bit
(if enabled)
CECLK
CEFP
ED[x]
EFP[x]
1
1
The Egress Interface is configured for the Clock Slave: EFP Enabled mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
ED[x] is sampled on the active edge of CECLK and EFP[x] is updated on the
falling edge of CECLK.