![](http://datasheet.mmic.net.cn/260000/PONE-000-01_datasheet_15945946/PONE-000-01_12.png)
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 12 of 56
PLSES Handshake Interrupt Generation
The PL-One firmware is supplied with an interrupt from the PLSES which is called the “PLSES Handshake
Interrupt”. This uses the standard 8052 INT0* interrupt. This means that the port bit P3.2 is no longer
available for the user application. P3.2 will normally read as 1, but will fall to 0 as soon as an interrupt is
generated from the PLSES. It will remain at 0 until the Ph_Confirm_Reg is read.
Note that this interrupt (INT0) MUST be set to the high priority level to ensure that no packets are lost. For
this interrupt to be properly configured, the following four bits need to be set:
PX0: Sets INT0 to high priority
IT0: INT0 triggers on a falling edge
EX0: INT0 is enabled
EA: Enable interrupts
The PLSES Handshake Interrupt is used by the PL-One firmware to perform its communication handshake
with the PLSES, and may indicate that valid data is present in the Ph_Rx_Buffer. It is provided by PLSES
based on some specific PLSES states and events. These are defined in Table 7. The Ph_Confirm_Reg
needs to always be read to determine the cause of the interrupt, and to process it accordingly.
The PLSES Handshake Interrupt is reset only after a PLSES Handshake Interrupt has been generated,
followed by the reading of the Ph_Confirm_Reg. Note that the PLSES Handshake Interrupt needs to have
been generated first, in order to distinguish between the Ph_Confirm_Reg being read by the user
application while in its main processing. This can be shown as follows:
1. PLSES Handshake Interrupt is generated
2. Ph_Confirm_Reg is read
3. The PLSES Handshake Interrupt is reset
Ph_Tx_Buffer
The Ph_Tx_Buffer is used to pass initialization parameters and data to be transmitted down to the PLSES.
Setting the
lzs
bit in Ph_Request_Reg will result in all leading zeros in this byte not being transmitted. To
simply transmit a field delimiter without any data symbols, this byte should be loaded with 00 hex, and
transmitted with leading zero suppression. The only exception to this is when transmitting the Preamble
field, in which case the contents of the Ph_Tx_Buffer have no effect on the Preamble which is transmitted.
Ph_Request_Reg
The Ph_Request_Reg is initialized with 00 hex following a hardware reset. The Ph_Request_Reg is read
and interpreted by the PLSES each time it is written to. This value is maintained until it is next written to by
the PL-One firmware. The various state transitions that can be brought about by writing to
Ph_Request_Reg are listed in Table 8.