參數(shù)資料
型號(hào)： PONE-000-01
廠商： Electronic Theatre Controls, Inc.
英文描述： The ideal device for simple nodes, such as switches, actuators and sensor
中文描述： 在簡(jiǎn)單的節(jié)點(diǎn)，如交換機(jī)，執(zhí)行器和傳感器的理想設(shè)備
文件頁(yè)數(shù)： 8/56頁(yè)
文件大小： 432K
代理商： PONE-000-01
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 8 of 56
M8052 to Physical Layer Interface
Even though the Physical Layer is also composed of the MDPS, the PL-One firmware only communicates
with the PLSES through 4 Special Function Registers (SFRs). The PLSES then communicates with the
MDPS if need be.
Power Line Symbol Encoding Sublayer (PLSES)
The main task of the PLSES is to encode/decode a sequence of symbols into/from a stream of states. In
addition, it has the task of recognizing the beginning of an incoming frame, and preventing a frame collision
when the PL-One firmware requests the channel for a transmission. Sometimes it must suppress leading
zeros in a given field before transmitting it, or restore them when receiving it. It also computes the CRC
checksum appended to the end of a frame while transmitting or receiving it to ensure communication
integrity. The PLSES will also detect Jabber conditions, defined as the transmission or reception of 1,000
consecutive SUPERIOR states on the medium, and indicates this via a PLSES Handshake Interrupt. A
timestamp can also be provided following any reception or transmission.
The PLSES operates in four main states: Initialization (INIT), Reception (RCV), Transmission (XMIT) and
Idle (IDLE). The RCV and XMIT states can be divided into sub-states as shown in Figure 3 State
Transition Diagram for PLSES.
The data travel between the PLSES and the M8052 through four Special Function Registers (SFRs). Each
one is 8-bit wide. They are denoted: Ph_Confirm_Reg, Ph_Request_Reg, Ph_Rx_Buffer and
Ph_Tx_Buffer. When a communication is requested by the PLSES to the PL-One firmware, an interrupt
(INT0) is sent to the M8052. The latter then reads the flags in the Ph_Confirm_Reg SFR to determine the
type of interrupt service routine to execute. The description of all flags is shown in Table 3. On the other
hand, when the PL-One firmware requests an action by the PLSES, the former writes a control value to the
Ph_Request_Reg. The description and the configuration of each of the control bits is shown in Table 6.
Data travels from the M8052 to the PLSES through the Ph_Tx_Buffer SFR one byte at a time. Similarly, the
data is read by the PL-One firmware through the Ph_Rx_Buffer SFR one byte at a time.
Ph_Rx_Buffer
It is used to pass on the packet Data symbols. It should be pointed out that when the Leading Zero
Suppression function has been carried out, the empty positions are padded with zeros. It is also used to
pass up both the reception and transmission timestamp bytes.
Ph_Confirm_Reg
The values of the 6 LSBits of this port are valid for exactly one read cycle after receiving a PLSES
Handshake Interrupt. When this port has been read once, the LSBits’ values will not necessarily be valid
until the next time a PLSES Handshake Interrupt is received. The 2 MSBits (
ch_active
and
ch_noisy
) of
this port are always valid.
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