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| 型號： | PONE-000-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The ideal device for simple nodes, such as switches, actuators and sensor |
| 中文描述： | 在簡單的節(jié)點，如交換機，執(zhí)行器和傳感器的理想設(shè)備 |
| 文件頁數(shù)： | 42/56頁 |
| 文件大小： | 432K |
| 代理商： | PONE-000-01 |
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March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 42 of 56
Interrupt Enable Register (IE)
For each bit in this register, a 1 enables the corresponding interrupt, and a 0 disables it. The allocation of
interrupts to bits is as follows:
IE.7
EA. Enable or disable all interrupt bits
IE.6
Not implemented
IE.5
ET2. Enable or disable Timer 2 interrupt
IE.4
ES. Enable or disable serial port interrupt
IE.3
ET1. Enable or disable Timer 1 overflow interrupt
IE.2
EX1. Enable or disable External interrupt 1
IE.1
ET0. Enable or disable Timer 0 overflow interrupt
IE.0
Ex0. Enable or disable PLSES interrupt
On reset, this register returns 00000000 binary.
Interrupt Priority Register (IP)
For each bit in this register, a 1 selects high priority for the corresponding interrupt, and a 0 selects low
priority. The allocation of interrupts to bits is as follows:
IP.7
Not implemented
IP.6
Not implemented
IP.5
PT2. Select priority for Timer 2 interrupt
IP.4
PS. Select priority for serial port interrupt
IP.3
PT1. Select priority for Timer 1 overflow interrupt
IP.2
PX1. Select priority for External interrupt 1
IP.1
PT0. Select priority for Timer 0 overflow interrupt
IP.0
Px0. Select priority for PLSES interrupt. This should always be set to 1 to ensure correct data
transfer between the 8052 and the PLSES.
When an interrupt is in progress, only a higher level interrupt can interrupt the service routine. On reset,
this register returns 00000000 binary.
Program Status Word (PSW)
This register contains status information resulting from CPU and ALU operation. The bit definitions are
given below:
PSW.7
CY. ALU carry flag
PSW.6
AC. ALU auxiliary carry flag
PSW.5
F0. General purpose user definable flag
PSW.4
RS1. Register bank select bit 1
PSW.3
RS0. Register bank select bit 0
PSW.2
OV. ALU overflow flag
PSW.1
F1. User definable flag
PSW.0
P. Parity flag. Set each instruction cycle to indicate odd/even parity in the accumulator
.
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