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| 型號： | PONE-000-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The ideal device for simple nodes, such as switches, actuators and sensor |
| 中文描述： | 在簡單的節(jié)點，如交換機，執(zhí)行器和傳感器的理想設(shè)備 |
| 文件頁數(shù)： | 51/56頁 |
| 文件大小： | 432K |
| 代理商： | PONE-000-01 |
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March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 51 of 56
OSCILLATOR CIRCUIT
The clock selector circuit (SELCLK pin) selects one divider to keep the PLSES frequency to 3.579545MHz,
regardless of the crystal selected (14.31818MHz or 21.47727MHz). To the M8052 section, the frequency
corresponds to the crystal selected.
SELCLK pin
0
1
Description
Use a 21.47727 MHz crystal
Use a 14.31818 MHz crystal
Table 18 Correspondance Between SELCLK Pin and Oscillator Frequency
RESET
Reset Synchronisation
The RESET* input pin is sampled in State 5 phase 2 of every machine cycle. When RST is sampled low, a
device reset is performed. The port pins will go into a high impedance state as soon as the RESET* goes
low. After RESET* is sampled high, it will take 1 or 2 clock cycles before ALE or PSEN are driven.
Reset Summary
The RST input performs the following functions:
The PC (Program Counter) is set to zero.
The DPTR (Data Pointer) is set to zero.
The Stack Pointer is set to 07 hex.
Register Bank zero is selected.
Ports 0, 1, 2, and 3 are set to input mode.
Interrupts are disabled.
All interrupt priorities are set low.
The Timer/Counters are stopped and the Timer Flags are cleared.
The Accumulator and B registers are set to zero.
The UART is disabled.
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