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March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 43 of 56
The register bank select bits operate as follows.
RS1
0
0
1
1
RS0
0
1
0
1
Register Bank Select
RB0. Registers from 00 - 07 hex.
RB1. Registers from 08 - 0F hex.
RB2. Registers from 10 - 17 hex.
RB3. Registers from 18 - 1F hex.
Table 13 Register Bank Selection Bits (PSW.4, PSW.3)
On reset, this register returns 00 hex.
Accumulator (ACC)
This register provides one of the operands for most ALU operations. In the instruction table below it is
denoted as "A".
On reset, this register returns 00 hex.
B Register (B)
This register provides the second operand for multiply or divide instructions. Otherwise it may be used as
a scratch pad register.
On reset, this register returns 00 hex.
INTERRUPTS
The M8052 provides 6 interrupt sources. The external interrupt INT1* is either level or edge triggered
(depending on bits in TCON, see above). Timer 0, 1 and 2 interrupts are generated by TF0, TF1 and TF2
via a rollover in their respective registers (or a negative transition on T2EX), except in mode 3 when TH0
controls timer 1 interrupt. The serial interrupt is generated by a logical OR of RI and TI. The Timer 2
interrupt is generated by the logical OR of TF2 and EXF2.
The CEWay PL-One uses the standard INT0* by the PLSES block, so this interrupt will not be accessible
via an external pin. Details on when this interrupt is generated are described in the PLSES section. All
other characteristics of the interrupt services are described in this section.
Interrupt Flag Clear
If the external interrupts are edge triggered, the interrupt flag is cleared on vectoring to the service routine,
but if they are level triggered then the flag is controlled by the external signal. Timer counter flags 0 and 1
are cleared on vectoring to the interrupt service routine, but the serial interrupt flag is not affected by
hardware. The serial interrupt flag and Timer 2 flag are not affected by hardware, they should be cleared by
software.
Priority Levels
One of two priority levels may be selected for each interrupt. A high priority interrupt may interrupt the
service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time the
higher level interrupt will be serviced first. An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is
observed as follows: