參數(shù)資料
型號： PONE-000-01
廠商： Electronic Theatre Controls, Inc.
英文描述： The ideal device for simple nodes, such as switches, actuators and sensor
中文描述： 在簡單的節(jié)點(diǎn)，如交換機(jī)，執(zhí)行器和傳感器的理想設(shè)備
文件頁數(shù)： 18/56頁
文件大?。?/td> 432K
代理商： PONE-000-01
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 18 of 56
State
Description
RCV_PRE_SYM
State
The PLSE Sublayer is in the process of receiving Preamble symbols,
which are encoded using Preamble USTs that are 114 microseconds
in length. This state counts the number of USTs in consecutive
INFERIOR or SUPERIOR states to decode each symbol. At each
received medium state transition (a SUPERIOR when LAST_RCV is
INFERIOR or an INFERIOR when LAST_RCV is SUPERIOR), the
symbol is decoded as “1” or “0” according to how many USTs elapsed
between state transitions. The state also waits for the Preamble EOF
(PEOF), which is 8 normal USTs in length (100
μ
s each.) In the case
where there are no Preamble symbols, e.g. an IACK frame, the
RCV_PRE_SYM state will only process and report the PEOF, and the
Ph_Confirm_Reg
bf/be
bit will not be set.
Transition
The SES block will go from RCV_PRE_SYM to RCV_SYM after it
receives 3 or more SUPERIOR 1s with 100-microsecond (1 UST)
spacing, and the medium state changes from SUPERIOR 1 to
SUPERIOR 2.
Transition
The SES block will go back to IDLE if it detects that the received
SUPERIOR state was noise (a SUPERIOR state followed by five
INFERIOR states), or if the Ph_Request_Reg
stop_rx
bit is set
RCV_SYM State
The PLSE Sublayer is in the process of receiving symbols within the
body of the frame. At each received medium state transition
(SUPERIOR 1 to SUPERIOR 2, or vice versa), the symbol is decoded
according to the elapsed time since the previous transition. The
symbol is stored in an 8-bit shift register in the SES block. When the
shift register is full, or an EOF (End of Field) or EOP (End of Packet)
symbol is received, the SES block will copy the data in the shift
register to Ph_Rx_Buffer, and send a PLSES Handshake Interrupt to
the PL-One firmware.
Transition
The SES will go to RCV_CRC after it receives an EOP symbol.
Transition
The SES will go to IDLE when the carrier is lost or when the
Ph_Request_Reg
stop_rx
bit is set. The carrier lost condition is
explained in a later section.
RCV_CRC State
The PLSE Sublayer is in the process of receiving CRC symbols. A bit
is shifted into the 16-bit CRC register for CRC computation every
UST. A received SUPERIOR 1 shifts in a 1, and a received
SUPERIOR 2 shifts in a 0. After 16 USTs, the Ph_Confirm_Reg
gd_packet
bit is set according to whether or not the frame has kept its
integrity during reception, and the SES will send a PLSES Handshake
Interrupt to the PL-One firmware.
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