參數(shù)資料
型號(hào): PONE-000-01
廠商: Electronic Theatre Controls, Inc.
英文描述: The ideal device for simple nodes, such as switches, actuators and sensor
中文描述: 在簡(jiǎn)單的節(jié)點(diǎn),如交換機(jī),執(zhí)行器和傳感器的理想設(shè)備
文件頁數(shù): 13/56頁
文件大?。?/td> 432K
代理商: PONE-000-01
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 13 of 56
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Ph_Request_Reg
stamp
tx_del
0
tx_del
1
reserved
Izs
stop_rx
hw_reset
tx
0
0
0
0
0
0
0
Table 5 Value to write to Ph_Request_Reg SFR to stop transmission and return to Idle state
Bits in Ph_Request_Reg
Description
Transmission. In IDLE state, it forces the PLSES to enter the XMIT state. In
XMIT state, it should always be high. In RCV state, it should always be low.
Hardware Reset. In all states, this bit forces the whole Physical Layer (PhyL) to
perform a hardware reset and return to the INIT state.
Stop reception. In the INIT state, it is set when passing initialization
parameters to the PLSE. In the RCV state, it forces the PLSES to stop reception
and enter the IDLE state.
Leading Zero Suppression. In the INIT state, it is set when passing
initialization parameters to the PLSE. In the XMIT state, it forces the PLSES to
suppress the leading zeros in the Ph_Tx_Buffer. When transitioning from the IDLE
to the XMIT_PRE_SYM state, it forces the PLSES to suppress the Preamble
symbols; in this case, only the PEOF is transmitted (e.g. for transmitting an IACK
or IRetry packets).
Reserved
Transmission delimiters. This pair of bits is used to select the type of
delimiter to transmit after the byte contained in Ph_Tx_Buffer. The mapping
between these bits and the possible delimiters is shown in Table 4.
Stamp. At the end of the RCV or XMIT states, this flag indicates to the PLSES that
the PL-One firmware needs one more significant timestamp byte (to a maximum
of four total) recorded when the last CRC symbol was received or transmitted.
Bit
tx
(MSB)
hw_reset
stop_rx
lzs
reserved
tx_del1
tx_del0
stamp
(LSB)
Table 6 Explanation of Bits in the Ph_Request_Reg SFR
State Transition Tables for Ph_Confirm_Reg and Ph_Request_Reg
The following two tables (Table 7 and Table 8) show the state transitions associated with the PLSES
Handshake Interrupts (reads of Ph_Confirm_Reg), and writes to Ph_Request_Reg.
Current State
Next State
Ph_Confirm
_Reg
1000 0000
Transition
IDLE
RCV_PRE_SYM
Detection of first SUPERIOR and
stop_rx
bit
not active.
After command to start transmission.
Ch_Quiet indication every UST.
XMIT_PRE_SYM
IDLE
XMIT_PRE_SYM
IDLE
0001 0000
0000 0000
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