參數(shù)資料
型號(hào): PONE-000-01
廠商: Electronic Theatre Controls, Inc.
英文描述: The ideal device for simple nodes, such as switches, actuators and sensor
中文描述: 在簡(jiǎn)單的節(jié)點(diǎn),如交換機(jī),執(zhí)行器和傳感器的理想設(shè)備
文件頁數(shù): 40/56頁
文件大?。?/td> 432K
代理商: PONE-000-01
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 40 of 56
T2CON.2
TR2. Run control bit for Timer 2. If set to 1, the timer is enabled.
T2CON.1
C/NT2. Timer/Counter select. A 0 selects internal timer mode. A 1 selects external counter
mode.
T2CON.0
CP/NRL2. Capture/Reload control. When set, captures occur on negative transitions of T2EX (if
EXEN2 is set). If 0, auto-reloads are performed on timer overflows or on negative transitions of T2EX (if
EXEN2 is set). If either RCLK or TCLK is 1, this bit is ignored and auto-reloads are performed on timer
overflows.
Timer/Counter 2 Data (TL2 TH2 RCAP2L RCAP2H)
TL2 and TH2 are the low and high bytes of timer/counter 2 respectively. RCAP2L and RCAP2H are the low
and high bytes of timer 2 capture registers. These registers are also used for auto-reload. TH2 and TL2
cannot be reliably read from or written to while Counter/Timer 2 is operating as a timer in either baud-rate
mode. Timer 2 should be turned off using T2CON before reading or writing to the counter registers in this
mode. On reset all these registers return 00 hex.
UART Registers
The UART uses two SFRs. SCON is the control register, SBUF the data register. Data is written to SBUF
for transmission, and SBUF is read to obtain received data. The received data and transmitted data
registers are completely independent. The bit definition for SCON follows.
UART Control (SCON)
SCON.7
SM0. UART mode specifier.
SCON.6
SM1. UART mode specifier.
SCON.5
SM2. UART mode specifier.
SCON.4
REN. If 1, enables reception. If 0, disables reception.
SCON.3
TB8. In modes 2 and 3, this is the 9th data bit sent.
SCON.2
RB8. In modes 2 and 3, this is the 9th data bit received. In mode 1, if SM2 = 0, this is the stop bit
received. In mode 0, this bit is not used.
SCON.1
TI. Transmit interrupt flag. This is set by hardware at the end of the 8th bit in mode 0, or at the
beginning of the stop bit in other modes. Must be cleared by software.
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